1、杭电计组实验9实现RI型指令的CPU设计实验实验报告 2018 年 6 月 1 日 成绩： 姓名阳光男学号16041321班级16052317专业计算机科学与技术课程名称计算机组成原理与系统结构试验任课老师张翔老师指导老师张翔老师机位号无实验序号9实验名称实验九 实现R-I型指令的CPU设计实验实验时间2018/6/2实验地点1教221实验设备号个人电脑 一、实验程序源代码顶层RI型指令CPU模块测试文件：module test; / Inputs reg rst; reg clk; / Outputs wire ZF; wire OF; wire 31:0 F; wire 31:0 M_R_
2、Data; / Instantiate the Unit Under Test (UUT) TOP_RI_CPU uut ( .rst(rst), .clk(clk), .ZF(ZF), .OF(OF), .F(F), .M_R_Data(M_R_Data) ); initial begin / Initialize Inputs rst = 0; clk = 0; / Wait 100 ns for global reset to finish #100; clk=1; / Add stimulus here forever begin #50; clk=clk; endend endmod
3、ule顶层LED验证模块：module TOP_LED(clk_100MHz,oclk,rst,SW,LED);input clk_100MHz;input oclk,rst;input 3:0SW;output reg7:0LED;wire rclk;wire ZF,OF;wire 31:0F;wire 31:0M_R_Data;xiaodou doudong(clk_100MHz,oclk,rclk);TOP_RI_CPU(clk_100MHz,rst,rclk,ZF,OF,F,M_R_Data);always(*)begincase(SW)3b0000:LED=F7:0;3b0001:L
4、ED=F15:8;3b0010:LED=F23:16;3b0011:LED=F31:24;3b0100:LED=M_R_Data7:0;3b0101:LED=M_R_Data15:8;3b0110:LED=M_R_Data23:16;3b0111:LED=M_R_Data31:24;3b1111:begin LED7:2=0;LED1=OF;LED0=ZF;enddefault:LED=0;endcaseendendmodule顶层RI型指令CPU模块module TOP_RI_CPU(input rst,input clk,output ZF,output OF,output 31:0F,o
5、utput 31:0M_R_Data);wire Write_Reg;wire 31:0Inst_code;wire 4:0rs;wire 4:0rt;wire 4:0rd;wire 31:0rs_data;wire 31:0rt_data;wire 31:0rd_data;wire 31:0imm_data;wire 15:0imm;wire rd_rt_s;wire imm_s;wire Mem_Write;wire alu_mem_s;wire 31:0W_Addr;wire 31:0W_Data;wire 31:0R_Data_A;wire 31:0R_Data_B;wire 31:0
6、F;wire 31:0ALU_B;wire 2:0ALU_OP;pc pc_connect(clk,rst,Inst_code);OP_YIMA op(Inst_code,ALU_OP,rs,rt,rd,Write_Reg,imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_mem_s);assign W_Addr=(rd_rt_s)?rt:rd;assign imm_data=(imm_s)?16imm15,imm:161b0,imm;Register_file R_connect(rs,rt,W_Addr,Write_Reg,W_Data,clk,rst,R_
7、Data_A,R_Data_B);assign ALU_B=(rt_imm_s)?imm_data:R_Data_B;ALU ALU_connect(R_Data_A,ALU_B,F,ALU_OP,ZF,OF);wire clk_tmp;wire d_outn;reg d_out=0;assign clk_tmp=clkd_out;assign d_outn=d_out;always(posedge clk_tmp)begin d_out=d_outn;endRAM_B Data_Mem ( .clka(clk_tmp), / input clka .wea(Mem_Write), / inp
8、ut 0 : 0 wea .addra(F5:0), / input 5 : 0 addra .dina(R_Data_B), / input 31 : 0 dina .douta(M_R_Data) / output 31 : 0 douta); assign W_Data=alu_mem_s?M_R_Data:F;endmodulePC取指令模块：module pc(input clk,input rst,output 31:0Inst_code);reg 31:0PC;wire31:0PC_new;initial PC=32h00000000;Inst_ROM Inst_ROM1 ( .
9、clka(clk), .addra(PC7:2), .douta(Inst_code) );assign PC_new=PC+4;always(negedge clk or posedge rst)begin if(rst) PC=32h00000000; else PC=24h000000,PC_new7:0;endendmoduleOP指令功能译码模块module OP_YIMA(inst,ALU_OP,rs,rt,rd,Write_Reg,imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_mem_s);input 31:0inst;output reg2:
10、0ALU_OP;output reg4:0rs;output reg4:0rt;output reg4:0rd;output reg Write_Reg;output reg15:0imm;output reg rd_rt_s;output reg imm_s;output reg rt_imm_s;output reg Mem_Write;output reg alu_mem_s;always(*)begin/R型指令if(inst31:26=6b000000)begin rd=inst15:11; rt=inst20:16; rs=inst25:21; alu_mem_s=0; Mem_W
11、rite=0; rd_rt_s=0; rt_imm_s=0; Write_Reg=(inst5:0=0)?1b0:1b1;case(inst5:0)6b100000:ALU_OP=3b100;6b100010:ALU_OP=3b101;6b100100:ALU_OP=3b000;6b100101:ALU_OP=3b001;6b100110:ALU_OP=3b010;6b100111:ALU_OP=3b011;6b101011:ALU_OP=3b110;6b000100:ALU_OP=3b111;endcaseend/I型立即数寻址指令if(inst31:29=3b001)beginimm=in
12、st15:0;rt=inst20:16;rs=inst25:21;Mem_Write=0;rd_rt_s=1;rt_imm_s=1;alu_mem_s=0;Write_Reg=1;case(inst31:26)6b001000:begin imm_s=1;ALU_OP=3b100;end6b001100:begin imm_s=0;ALU_OP=3b000;end6b001110:begin imm_s=0;ALU_OP=3b010;end6b001011:begin imm_s=0;ALU_OP=3b110;endendcaseend/I型取数/存数指令if(inst31:30=2b10)&
13、(inst28:26=3b011)beginimm=inst15:0;rt=inst20:16;rs=inst25:21;rd_rt_s=1;rt_imm_s=1;imm_s=1;case(inst31:26)6b100011:begin alu_mem_s=1;Mem_Write=0;Write_Reg=1;ALU_OP=3b100;end6b101011:begin Mem_Write=1; Write_Reg=0;ALU_OP=3b100;endendcaseendendendmodule寄存器堆模块：Module Register_file(R_Addr_A,R_Addr_B,W_Ad
14、dr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input 4:0R_Addr_A;input 4:0R_Addr_B;input 4:0W_Addr;input Write_Reg;input 31:0W_Data;input Clk;input Reset;output 31:0R_Data_A;output 31:0R_Data_B;reg 31:0REG_Files0:31;reg 5:0i;initial/仿真过程中的初始化begin for(i=0;i=31;i=i+1) REG_Filesi=0;endassign R_Data_
15、A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset)begin if(Reset) for(i=0;i=31;i=i+1) REG_Filesi=0; else if(Write_Reg&W_Addr!=0) REG_FilesW_Addr=W_Data; end endmoduleALU运算模块：module ALU(A,B,F,ALU_OP,ZF,OF);input 31:0A,B;input 2:0ALU_OP;output reg ZF,OF;output r
16、eg31:0F;reg C32;always(*)begin OF=1b0; C32=1b0; case(ALU_OP) 3b000:F=A&B; 3b001:F=A|B; 3b010:F=AB; 3b011:F=(AB); 3b100:begin C32,F=A+B;OF=A31B31F31C32;end 3b101:begin C32,F=A-B;OF=A31B31F31C32;end 3b110: if(AB) F=1; else F=0; 3b111:F=BA; endcase if(F=0) ZF=1; else ZF=0; end endmodule时钟按键消抖代码：module
17、xiaodou( input clk_100MHz, input BTN, output reg BTN_Out ); reg BTN1,BTN2; wire BTN_Down; reg 21:0 cnt; reg BTN_20ms_1,BTN_20ms_2; wire BTN_Up; always (posedge clk_100MHz) begin BTN1 = BTN; BTN2 = BTN1; end assign BTN_Down = (BTN2)& BTN1 ; /从0到1的跳变 always (posedge clk_100MHz) begin if (BTN_Down) beg
18、in cnt = 22b0; BTN_Out = 1b1; end else cnt = cnt+1b1; if (cnt=22h20000) BTN_20ms_1 = BTN; BTN_20ms_2 = BTN_20ms_1; if (BTN_Up) BTN_Out = 1b0; end assign BTN_Up = BTN_20ms_2 & (BTN_20ms_1);/从1到0 endmodule二、仿真波形三、电路图 顶层电路模块 顶层电路内部结构 四、引脚配置（约束文件）NET LED7 LOC = T11;NET LED6 LOC = R11;NET LED5 LOC = N11;
19、NET LED4 LOC = M11;NET LED3 LOC = V15;NET LED2 LOC = U15;NET LED1 LOC = V16;NET LED0 LOC = U16;NET SW3 LOC = M8;NET SW2 LOC = V9;NET SW1 LOC = T9;NET SW0 LOC = T10;NET rst LOC = C4;NET clk_100MHz LOC = V10;NET oclk LOC = C9;五、思考与探索（1）R-I型指令CPU实验结果记录表序号 指令 执行结果 标志 结论 1 38011234 0000_1234 0 0 正确 2 200
20、26789 0000_6789 0 0 正确 3 20039000 FFFF_9000 0 0 正确 4 38040010 0000_0010 0 0 正确 5 00822804 6789_0000 0 0 正确 6 00253025 6789_1234 0 0 正确 7 00833804 9000_0000 0 0 正确 8 00464020 6789_79BD 0 0 正确 9 00414822, 0000_5555 0 0 正确 10 00225022 FFFF_AAAB 0 0 正确 11 206b7fff 0000_0FFF 0 0 正确 12 206c8000 FFFF_1000 0 0 正确 13 314dffff 0000_AAAB 0 0 正确 14 2c4e6788 0000_0000 0 0 正确 15 2c4f678a 0000_0001 0 0 正确 16 ac0c0014 0000_0FFF 0 0 正确
