1、 .clk(clk), .ZF(ZF), .OF(OF), .F(F), .M_R_Data(M_R_Data) ); initial begin / Initialize Inputs rst = 0; clk = 0; / Wait 100 ns for global reset to finish #100; clk=1; / Add stimulus here forever begin #50; clk=clk; endendendmodule顶层LED验证模块:module TOP_LED(clk_100MHz,oclk,rst,SW,LED);input clk_100MHz;i
2、nput oclk,rst;input 3:0SW;output reg7:0LED;wire rclk;wire ZF,OF;wire 31:0F;0M_R_Data;xiaodou doudong(clk_100MHz,oclk,rclk);TOP_RI_CPU(clk_100MHz,rst,rclk,ZF,OF,F,M_R_Data);always(*)begincase(SW)3b0000:LED=F7:0;b0001:LED=F15:8;b0010:LED=F23:16;b0011:LED=F31:24;b0100:LED=M_R_Data7:b0101:LED=M_R_Data15
3、:b0110:LED=M_R_Data23:b0111:LED=M_R_Data31:b1111:begin LED7:2=0;LED1=OF;LED0=ZF;default:LED=0;endcase顶层RI型指令CPU模块module TOP_RI_CPU(input rst,input clk,output ZF,output OF,output 31:0F,output 31:0M_R_Data);wire Write_Reg;0Inst_code;wire 4:0rs;0rt;0rd;0rs_data;0rt_data;0rd_data;0imm_data;wire 15:0imm;
4、wire rd_rt_s;wire imm_s;wire Mem_Write;wire alu_mem_s;0W_Addr;0W_Data;0R_Data_A;0R_Data_B;0ALU_B;wire 2:0ALU_OP;pc pc_connect(clk,rst,Inst_code);OP_YIMA op(Inst_code,ALU_OP,rs,rt,rd,Write_Reg,imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_mem_s);assign W_Addr=(rd_rt_s)?rt:rd;assign imm_data=(imm_s)?16imm1
5、5,imm:161b0,imm;Register_file R_connect(rs,rt,W_Addr,Write_Reg,W_Data,clk,rst,R_Data_A,R_Data_B);assign ALU_B=(rt_imm_s)?imm_data:R_Data_B;ALU ALU_connect(R_Data_A,ALU_B,F,ALU_OP,ZF,OF);wire clk_tmp;wire d_outn;reg d_out=0;assign clk_tmp=clkd_out;assign d_outn=d_out;always(posedge clk_tmp) d_out=d_o
6、utn;RAM_B Data_Mem ( .clka(clk_tmp), / input clka .wea(Mem_Write), / input 0 : 0 wea .addra(F5:0), / input 5 : 0 addra .dina(R_Data_B), / input 31 : 0 dina .douta(M_R_Data) / output 31 : 0 douta); assign W_Data=alu_mem_s?M_R_Data:F;PC取指令模块:module pc(input clk,input rst,output 31:0Inst_code);reg 31:0
7、PC;wire31:0PC_new;initial PC=32h00000000;Inst_ROM Inst_ROM1 ( .clka(clk), .addra(PC7:2), .douta(Inst_code) assign PC_new=PC+4;always(negedge clk or posedge rst) if(rst) PC=32 else PC=24h000000,PC_new7:0;OP指令功能译码模块module OP_YIMA(inst,ALU_OP,rs,rt,rd,Write_Reg,imm,rd_rt_s,imm_s,rt_imm_s,Mem_Write,alu_
8、mem_s);input 31:0inst;output reg2:output reg4:output reg Write_Reg;output reg15:output reg rd_rt_s;output reg imm_s;output reg rt_imm_s;output reg Mem_Write;output reg alu_mem_s;/R型指令if(inst31:26=6b000000) rd=inst15:11; rt=inst20: rs=inst25:21; alu_mem_s=0; Mem_Write=0; rd_rt_s=0; rt_imm_s=0; Write_
9、Reg=(inst5:0=0)?1b0:b1;case(inst5:0)6b100000:ALU_OP=3b100;b100010:b101;b100100:b000;b100101:b001;b100110:b010;b100111:b011;b101011:b110;b000100:b111;/I型立即数寻址指令29=3b001)imm=inst15:rt=inst20:rs=inst25:Mem_Write=0;rd_rt_s=1;rt_imm_s=1;alu_mem_s=0;Write_Reg=1;case(inst31:26)b001000:begin imm_s=1;b001100
10、:begin imm_s=0;b001110:b001011:/I型取数/存数指令if(inst31:30=2b10)&(inst28:26=3b011)imm_s=1;b100011:begin alu_mem_s=1;begin Mem_Write=1; Write_Reg=0;寄存器堆模块:Module Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);input 4:0R_Addr_A;0R_Addr_B;input Write_Reg;input Clk;input
11、 Reset;output 31:0REG_Files0:31;reg 5:0i;initial/仿真过程中的初始化 for(i=0;i=31;i=i+1) REG_Filesi=0;assign R_Data_A=REG_FilesR_Addr_A;assign R_Data_B=REG_FilesR_Addr_B;always(posedge Clk or posedge Reset) if(Reset) if(Write_Reg&W_Addr!=0) REG_FilesW_Addr=W_Data; end endmoduleALU运算模块:module ALU(A,B,F,ALU_OP,
12、ZF,OF);0A,B;input 2:output reg ZF,OF;output reg31:reg C32; OF=1b0; C32=1 case(ALU_OP) 3b000:F=A&B;b001:F=A|B;b010:F=AB;b011:F=(AB);b100:begin C32,F=A+B;OF=A31B31F31C32;b101:begin C32,F=A-B;b110: if(AB) F=1; else F=0;b111:F=BA; endcase if(F=0) ZF=1; ZF=0;时钟按键消抖代码:module xiaodou( input clk_100MHz, inp
13、ut BTN, output reg BTN_Out reg BTN1,BTN2; wire BTN_Down; reg 21:0 cnt; reg BTN_20ms_1,BTN_20ms_2; wire BTN_Up; always (posedge clk_100MHz) begin BTN1 = BTN; BTN2 = BTN1; assign BTN_Down = (BTN2)& BTN1 ; /从0到1的跳变 if (BTN_Down) cnt = 22 BTN_Out = 1 else cnt = cnt+1 if (cnt=22h20000) BTN_20ms_1 BTN_20m
14、s_2 = BTN_20ms_1; if (BTN_Up) BTN_Out assign BTN_Up = BTN_20ms_2 & (BTN_20ms_1);/从1到0二、仿真波形三、电路图 顶层电路模块 顶层电路内部结构四、引脚配置(约束文件)NET LED7 LOC = T11;LED6 LOC = R11;LED5 LOC = N11;LED4 LOC = M11;LED3 LOC = V15;LED2 LOC = U15;LED1 LOC = V16;LED0 LOC = U16;SW3 LOC = M8;SW2 LOC = V9;SW1 LOC = T9;SW0 LOC = T10
15、;rst LOC = C4;clk_100MHz LOC = V10;oclk LOC = C9;五、思考与探索(1)R-I型指令CPU实验结果记录表序号 指令 执行结果 标志 结论 1 38011234 0000_1234 0 0 正确 2 20026789 0000_6789 0 0 正确 3 20039000 FFFF_9000 0 0 正确 4 38040010 0000_0010 0 0 正确 5 00822804 6789_0000 0 0 正确 6 00253025 6789_1234 0 0 正确 7 00833804 9000_0000 0 0 正确 8 00464020 6789_79BD 0 0 正确 9 00414822, 0000_5555 0 0 正确 10 00225022 FFFF_AAAB 0 0 正确 11 206b7fff 0000_0FFF 0 0 正确 12 206c8000 FFFF_1000 0 0 正确 13 314dffff 0000_AAAB 0 0 正确 14 2c4e6788 0000_0000 0 0 正确 15 2c4f678a 0000_0001 0 0 正确 16 ac0c0014 0000_0FFF 0 0 正确