1、函数发生器是一种很常用的器件，在很多情况下，最常用的波形是正弦波，方波，三角波，递增，递减斜波和阶梯波六种。虽然用模拟电子线路很容易得到这些波形，但是这种方法会使硬件线路较为繁琐，而且模拟线路会受到干扰。本设计采用综合设计方法使用FPGA来实现智能函数发生器，它由六个波形产生模块及波形选择输出模块组成，波形选择模块的输出q接在D/A转换的数据端，就可以在D/A输出端得到想要的其中之一的任一种光滑的波形五、课程设计摘要（英文）：The function generator is one kind of very commonly used component, In very many situ
2、ations,The most commonly used profile is a sine wave,Square-wave,Triangle wave,Increases progressively,Decreases progressively the wave tilt and the steps and ladders wave six kinds. Although is very easy with the simulation electronic circuit to obtain these profiles, But this method can cause the
3、hardware line to be tedious,Moreover the artificial line can receive the disturbance. This design uses FPGA to realize the intelligence function generator,It has the module and the profile choice output module by six profiles is composed, Profile choice module output q meets in D/A transforms data e
4、nd, May in the D/A out-port obtains one of them which wants no matter what one kind of smooth profile.正文一、设计思路1.基于QUASTUS II平台，采用VHDL语言，设计一波形信号发生器。首先根据对各波形的幅度进行采样，获得各波形的波形数据表，使用FPGA来实现智能函数发生器，它由六个波形产生模块及波形选择输出模块组成，然后FPGA根据输入的时钟（频率可根据要求可变）作为地址信号，从FPGA数据线上输出相应的波形数据，再送入实验板上的D/A转换芯片进行转换为模拟信号，最后送入滤波电路滤波后
5、输出，就可以得到想要的任意其中的一个波形二、设计输入文件与调试分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity fenpin isport （clk: in std_logic; clkfen: out std_logic）;end fenpin;architecture fenpin of fenpin issignal clk_mid: std_logic;begin process（clk） variable data:integer range 0 to 99; begin
6、 if clkevent and clk=1 then if data=99 then data:=0; clk_mid=not clk_mid; else =data+1;end if;clkfen=clk_mid;end process;2.递减波形数据产生模块设计LIBRARY IEEE;USE IEEE. STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY dj IS PORT （clk,reset: IN STD_LOGIC; q:OUT STD_LOGIC_VECTOR （7 DOWNTO 0）;END dj;ARC
7、HITECTURE behave OF dj ISBEGIN PROCESS （clk,reset） VARIABLE tmp: STD_LOGIC_VECTOR （7 DOWNTO 0）; BEGIN IF reset=0THEN tmp:=11111111; ELSIF clkEVENT AND clk= IF tmp=00000000 Tmp: ELSE=tmp-1; END IF;END IF; q=tmp;END PROCESS;END behave;3.递增（锯齿波）波形数据产生模块设计LIBRARY IEEE;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENT
8、ITY dz IS END dz;ARCHITECTURE behave OF dz IS=tmp+1;q END PROCESS;4.方波波形数据产生模块设计ENTITY fb ISOUT INTEGER RANGE 0 TO 255）;END fb;ARCHITECTURE behave OF fb ISSIGNAL a: BIT; VARIABLE cnt: INTEGER range 0 to 31; A= IF cnt31 THENCnt:=cnt+1; cnt: a=NOT a; Process （clk,a）IF clk IF a= Q=255;END behave；5.三角波波
9、形数据产生模块设计ENTITY jcb IS END jcb;ARCHITECTURE behave OF jcb IS VARIABLE a: STD_LOGIC;IF tmp=11111110 a:ELSE00000001END behave6.阶梯波形数据产生模块设计entity jtb isport（clk,reset:in std_logic;q:out std_logic_vector（7 downto 0）;end jtb;architecture a of jtb isprocess（clk,reset）variable tmp:std_logic_vector（7 downt
10、o 0）;if reset=tmp:else if clkif tmp=else=tmp+16;end a;7.正弦波波形数据产生模块设计use ieee.std_logic_arith.all;entity zx is port（clk: reset:end zx;architecture behav of zx is signal b:integer range 0 to 63; signal d:integer range 0 to 255;process（clk）begin if reset=then b elsif clk if b=63 then b else bd=254; wh
11、en 02=252; when 03=249;when 04=245; when 05=239; when 06=233; when 07=225;when 08=217; when 09=207; when 10=197; when 11=186;when 12=174; when 13=162; when 14=150; when 15=137;when 16=124; when 17=112;when 18=99; when 19=87; when 20=75; when 21=64; when 22=53; when 23=43; when 24=34; when 25=26; whe
12、n 26=19; when 27=13;when 28=8; when 29=4;when 30=1; when 31=when 32= when 33=when 34= when 35=when 36= when 37= when 38= when 39=when 40= when 41= when 42= when 43=when 44= when 45= when 46= when 47=when 48= when 49= when 50= when 51=when 52= when 53= when 54= when 55=when 56= when 57= when 58= when
13、 59=when 60= when 61= when 62= when 63=when others=null; end case;=conv_std_logic_vector（d,8）;end behav;8.六选一选择器模块设计ENTITY xz IS PORT （sel: IN STD_LOGIC_VECTOR （2 DOWNTO 0）; d0,d1,d2,d3,d4,d5: IN STD_LOGIC_VECTOR（7 DOWNTO 0）; OUT STD_LOGIC_VECTOR（7 DOWNTO 0）;END xz;ARCHITECTURE behave OF xz IS PROCE
14、SS （sel） CASE sel IS WHEN 000 =d0;001=d1;010=d2;011=d3;100=d4;101=d5; WHEN OTHERS =NULL; END CASE; END behave;9译码use ieee.numeric_std.all;entity ym is port（ clk,rst : data :in std_logic_vector（7 downto 0）; sel :out std_logic_vector（2 downto 0）; data_disp:out std_logic_vector（6 downto 0）;end ym;archi
15、tecture RTL of ym issignal count :integer range 9 downto 0;signal temp :integer range 4 downto 0;signal number_h,number_t,number_l:integer range 0 to 9;process（data,clk,rst）if（rst=）then number_h number_t number_l=200 AND to_integer（unsigned（data）-200=50）then=2;=5;=to_integer（unsigned（data）-250;=40）thennumber_l=90）then=9;=to_integer（unsigned（data）- 190;=80）then=to_integer（unsigned（data）-180;=70）then=7;=to_integer（unsigned（data）-170;=60）then=6;=to_integer（unsigned（data）-160;=to_integer（unsigned（data）-150; 140;=to_integer（unsigned（data）-130;
