1、21按键简易电子琴可自动播放乐曲知识讲解21按键简易电子琴可自动播放乐曲课程设计报告课程名称:FPGA课程设计 (EDA技术及应用) 题 目:基于FPGA的简易电子琴设计学 院: 物理与电子工程学院 专 业: 电 子 信 息 工 程 班 级: 学 号: 学生姓名:指导教师: 起讫日期: 基于FPGA的简易电子琴设计物理与电子工程学院 电子信息工程 1 设计目的任务及要求1 简易电子琴1) 设计一个能发出7个音阶的系统并能多种模式播放歌曲(歌曲可自定,至少3首)2) 利用一基准脉冲产生1,2,3,。共7个音阶信号,进行弹奏;3) 用指示灯显示节拍;4) *能对弹奏乐曲存储并回放。1.1设计目的1
2、、熟悉VHDL语言2、学习电子琴的设计,调试,仿真以及对仿真波形的调试1.2设计要求(简易电子琴的功能)1、设计一个能发出7个音阶的系统并能多种模式播放歌曲(歌曲可自定,至少首)2、 利用一基准脉冲产生1,2,3,。共7个音阶信号,进行弹奏;3、 用指示灯显示节拍;4、 *能对弹奏乐曲存储并回放。2、设计内容自动播放Notetabs二选一选择器mux21c分频预置数ToneTabs一)、设计思路按 键 输 入按键输入判断ceshi按键去抖动FEN按 键 输 出SWI分频器SPEAKER发出音乐spkout二)、设计实现本设计实现了能发出底、中、高三个节拍的7个音阶的系统,整个系统共有3首歌曲,
3、这三首歌曲具有顺序播放和随机切换歌曲的播放功能。能随意弹奏每首歌曲,同时具有数码管显示每个音阶所对应的阿拉伯数字,不同的节拍我们也有相应的指示灯作为区分,在低音时无指示灯亮,中音时有一个亮,高音时有两个指示灯亮。1)按键输入的判断:a.代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ceshi ISPORT(s: IN STD_LOGIC; Y:out std_logic);END ENTITY ceshi;ARCHITECTURE FUN OF ceshi ISbeginPRO
4、CESS(s)BEGIN IF s=1 THEN Y =1; ELSE y=0; end if; end process; END ARCHITECTURE FUN;b.波形仿真图2)按键去抖动a.代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FEN ISPORT(CLK,KIN:IN STD_LOGIC; KOUT:OUT STD_LOGIC);END;ARCHITECTURE BHV OF FEN ISSIGNAL KL,KH:STD_LOGIC_VECTOR(3 DOWN
5、TO 0);BEGINPROCESS(CLK,KIN,KL,KH) BEGINIF CLKEVENT AND CLK=1 THENIF(KIN=0) THEN KL=KL+1;ELSE KL=0000;END IF;IF(KIN=1) THEN KH=KH+1;ELSE KH1100) THEN KOUT0111) THEN KOUT=0;END IF;END IF;END PROCESS;END;b.波形仿真图3)产生节拍控制和音阶选择信号a.代码3)音乐自动播放LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIG
6、NED.ALL;ENTITY NOTETABS ISPORT(CLK : IN STD_LOGIC; S : IN STD_LOGIC_VECTOR(1 DOWNTO 0); TONEINDEX : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0);END ENTITY NOTETABS;ARCHITECTURE FUN OF NOTETABS ISCOMPONENT MUSIC PORT ( address : IN STD_LOGIC_VECTOR (8 DOWNTO 0); clock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR
7、(4 DOWNTO 0) );END COMPONENT;SIGNAL COUNTER : STD_LOGIC_VECTOR(8 DOWNTO 0);BEGINPROCESS(CLK,COUNTER)BEGIN IF (COUNTER=432) THEN COUNTER=000000000; ELSIF (CLKEVENT AND CLK =1) THEN COUNTER144) THEN COUNTER=000000000; ELSIF(S=10 AND (COUNTER 288) THEN COUNTER=010010000; ELSIF (S=01 AND (COUNTER 432) T
8、HEN COUNTERCOUNTER,q=TONEINDEX,clock=CLK); END ARCHITECTURE FUN;b.波形仿真图4)二选一选择器a.代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21c IS PORT(k_code,toneindex:IN STD_LOGIC_VECTOR(4 DOWNTO 0); key:IN STD_LOGIC; index:OUT STD_LOGIC_VECTOR(4 DOWNTO 0); END;ARCHITECTURE five OF mux21c IS BEGIN PROCE
9、SS(k_code,toneindex,key) BEGIN IF key=1 THEN index=k_code; ELSE index=toneindex; END IF; END PROCESS; END five;b.波形仿真图5)按键的输出a.代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SWI ISPORT(A,B,C,D,E,F,G ,H,I,K,L,M,N,O,P,Q,R,S,T,U: IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0);END ENTITY SWI;ARC
10、HITECTURE FUN OF SWI ISSIGNAL J : STD_LOGIC_VECTOR( 19 DOWNTO 0);BEGINJ Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y NULL;END CASE;END PROCESS P1;END ARCHITECTURE FUN;b.波形仿真图6)分频预置数的产生a.代码LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY ToneTaba IS PORT ( Index : IN STD_LOGIC_VECTOR (4 DOWNTO 0); CODE
11、: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); HIGH1,HIGH2 : OUT STD_LOGIC; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0);END; ARCHITECTURE one OF ToneTaba IS BEGIN Search : PROCESS(Index) BEGIN CASE Index IS WHEN 00000 = Tone=11111111111; CODE=0000; HIGH1 =0;HIGH2 Tone=01100000101; CODE=0001; HIGH1 =0;HIGH2 Tone
12、=01110010000; CODE=0010; HIGH1 =0;HIGH2 Tone=10000001100; CODE=0011; HIGH1 =0;HIGH2 Tone=10001000100; CODE=0100; HIGH1 =0;HIGH2 Tone=10010101101; CODE=0101; HIGH1 =0;HIGH2 Tone=10100001010; CODE=0110; HIGH1 =0;HIGH2 Tone=10101011100; CODE=0111; HIGH1 =0;HIGH2 Tone=10110000010; CODE=0001; HIGH1 =1;HI
13、GH2 Tone=10111001000; CODE=0010; HIGH1 =1;HIGH2 Tone=11000000110; CODE=0011; HIGH1 =1;HIGH2 Tone=11000100010; CODE=0100; HIGH1 =1;HIGH2 Tone=11001010110; CODE=0101; HIGH1 =1;HIGH2 Tone=11010000100; CODE=0110; HIGH1 =1;HIGH2 Tone=11010011010; CODE=0111; HIGH1 =1;HIGH2 Tone=11011000000; CODE=0001; HIG
14、H1 =1;HIGH2 Tone=11011100100; CODE=0010; HIGH1 =1;HIGH2 Tone=11100000011; CODE=0011; HIGH1 =1;HIGH2 Tone=11100010001; CODE=0100; HIGH1 =1;HIGH2 Tone=11100001011; CODE=0101; HIGH1 =1;HIGH2 Tone=11101000010; CODE=0110; HIGH1 =1;HIGH2 Tone=11101001100; CODE=0111; HIGH1 =1;HIGH2 NULL; END CASE; END PROC
15、ESS; END;b.波形仿真图7)分频器a.代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY SPEAKER ISPORT(CLK : IN STD_LOGIC; TONE : IN STD_LOGIC_VECTOR(10 DOWNTO 0); SPKS : OUT STD_LOGIC);END ENTITY SPEAKER;ARCHITECTURE FUN OF SPEAKER ISSIGNAL PRECLK,FULLSPKS : STD_LOGIC; BEGIN PROCES
16、S(CLK) VARIABLE COUNT4 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PRECLK11 THEN PRECLK=1;COUNT4 :=0000; ELSIF CLKEVENT AND CLK = 1 THEN COUNT4:=COUNT4+1; END IF; END PROCESS; PROCESS(PRECLK,TONE) VARIABLE COUNT11 : STD_LOGIC_VECTOR(10 DOWNTO 0); BEGIN IF PRECLKEVENT AND PRECLK =1 THEN IF COUNT11 = 16#7FF
17、# THEN COUNT11 := TONE ;FULLSPKS=1; ELSE COUNT11 := COUNT11+1;FULLSPKS=0; END IF;END IF;END PROCESS;PROCESS(FULLSPKS) VARIABLE COUNT2 : STD_LOGIC; BEGIN IF FULLSPKSEVENT AND FULLSPKS= 1 THEN COUNT2 := NOT COUNT2; IF COUNT2 = 1 THEN SPKS=1; ELSE SPKS =0; END IF;END IF;END PROCESS;END ARCHITECTURE FUN;b.波形仿真图3、系统仿真与调试A、原理图:B、波形仿真C、PCB图:D、调试图:5、 主要参考文献1 潘松 黄继业 EDA技术实用数据VHDL版(第五版) 科学出版社 20132 曹昕燕,周凤臣.EDA技术实验与课程设计.清华大学出版社,2006.3 阎石,数学电子技术基础.高等教育出版社,2003.