SDRSDRAM控制器白皮书中英文对照版本.docx
- 文档编号:10297545
- 上传时间:2023-05-24
- 格式:DOCX
- 页数:22
- 大小:477.99KB
SDRSDRAM控制器白皮书中英文对照版本.docx
《SDRSDRAM控制器白皮书中英文对照版本.docx》由会员分享,可在线阅读,更多相关《SDRSDRAM控制器白皮书中英文对照版本.docx(22页珍藏版)》请在冰点文库上搜索。
SDRSDRAM控制器白皮书中英文对照版本
SDRSDRAM控制器白皮书中英文对照版
翻译:
合肥工业大学检测技术研究所彭良清(peng6602@)日期:
2004/4/24
原文:
Introduction
Thesingledatarate(SDR)synchronousdynamicrandomaccessmemory(SDRAM)controllerprovidesasimplifiedinterfacetoindustrystandardSDRSDRAM.TheSDRSDRAMControllerisavailableineitherVerilogHDLorVHDLandisoptimizedfortheAltera®APEX™architecture.TheSDRSDRAMControllersupportsthefollowingfeatures:
⏹Burstlengthsof1,2,4,or8datawords
⏹CASlatencyof2or3clockcycles
⏹16-bitprogrammablerefreshcounterusedforautomaticrefresh
⏹2-chipselectsforSDRAMdevices
⏹SupportstheNOP,READA,WRITEA,AUTO_REFRESH,PRECHARGE,ACTIVATE,URST_STOP,andLOAD_MRcommands
⏹Supportforfull-pagemodeoperation
⏹Datamasklineforwriteoperations
⏹PLLtoincreasesystemperformance
⏹Supportfordata-pathwidthsof16,32,and64bits
Figure1showsasystem-leveldiagramoftheSDRSDRAMController.
SDRAMOverview
SDRAMishigh-speeddynamicrandomaccessmemory(DRAM)withasynchronousinterface.Thesynchronousinterfaceandfully-pipelinedinternalarchitectureofSDRAMallowsextremelyfastdataratesifusedefficiently.Internally,SDRAMdevicesareorganizedinbanksofmemory,whichareaddressedbyrowandcolumn.Thenumberofrow-andcolumn-addressbitsandthenumberofbanksdependsonthesizeofthememory.SDRAMiscontrolledbybuscommandsthatareformedusingcombinationsoftheRASN,CASN,andWENsignals.Forinstance,onaclockcyclewhereallthreesignalsarehigh,theassociatedcommandisanooperation(NOP).ANOPisalsoindicatedwhenthechipselectisnotasserted.Table1showsthestandardSDRAMbuscommands.
表1.SDRAM总线命令
命令
缩写
RASN
CASN
WEN
Nooperation
NOP
H
H
H
Active
ACT
L
H
H
Read
RD
H
L
H
Write
WR
H
L
L
Burstterminate
BT
H
H
L
Precharge
PCH
L
H
L
Autorefresh
ARF
L
L
H
Loadmoderegister
LMR
L
L
L
SDRAMbanksmustbeopenedbeforearangeofaddressescanbewrittentoorreadfrom.TherowandbanktobeopenedareregisteredcoincidentwiththeACTcommand.Whenabankisaccessedforareadorawriteitmaybenecessarytoclosethebankandre-openitiftherowtobeaccessedisdifferentthantherowthatiscurrentlyopened.ClosingabankisdonewiththePCHcommand.
SDRAM
TheprimarycommandsusedtoaccessSDRAMareRDandWR.WhentheWRcommandisissued,theinitialcolumnaddressanddatawordisregistered.WhenaRDcommandisissued,theinitialaddressisregistered.Theinitialdataappearsonthedatabus1to3clockcycleslater.ThisisknownasCASlatencyandisduetothetimerequiredtophysicallyreadtheinternalDRAMcoreandregisterthedataonthebus.TheCASlatencydependsonthespeedoftheSDRAMandthefrequencyofthememoryclock.Ingeneral,thefastertheclock,themorecyclesofCASlatencyarerequired.AftertheinitialRDorWRcommand,sequentialreadandwritescontinueuntiltheburstlengthisreachedoraBTcommandisissued.SDRAMmemorydevicessupportburstlengthsof1,2,4,or8datacycles.TheARFisissuedperiodicallytoensuredataretention.ThisfunctionisperformedbytheSDRSDRAMControllerandistransparenttotheuser.
FunctionalDescription
Table2showstheSDRSDRAMControllerinterfacesignals.AllsignalsaresynchronoustothesystemclockandoutputsareregisteredattheSDRSDRAMController’soutputs.
信号
名称
激活电平
I/O
描述
CLK
时钟
NA
Input
系统时钟
RESET_N
复位
Low
Input
系统复位
ADDR[ASIZE-1:
0]
存储器地址
NA
Input
读或者写时的存储器地址,地址宽度由ASIZE.设置
CMD[2:
0]
命令
NA
Input
命令请求
CMDACK
命令应答
High
Output
命令请求的响应
DATAIN[DSIZE-1:
0]
输入数据
NA
Input
输入数据总线,宽度由DSIZE设置
DATAOUT[DSIZE-1:
0]
输出数据
NA
Output
数据数据总线,宽度由DSIZE设置
DM[(DSIZE/8)-1:
0]
数据屏蔽
High
Input
Masksindividualbytesduringdatawrite
SA[11:
0]
地址总线
NA
Output
SA[11:
0]信号在ACT命令发出时锁存到行地址中,SA[n:
0]在RD/WR命令期间锁存到列地址中,其中“n”值取决于使用的SDRAM容量,SA[10]信号在PCH命令时被采样,该信号决定是否对所有存储体还是对指定存储器(由信号BA[1:
0]决定)进行预充电。
地址输出在LMR命令时提供操作码。
BA[1:
0]
体选地址
NA
Output
该信号决定了在ACT,RD,WR,或PCH命令时,选择那个存储体。
CS_N[1:
0]
片选
Low
Output
SDRAMchipselects.
SDRAM片选信号,
CKE
时钟使能
High
Output
SDRAM的CKE信号输入
RAS_N
行地址选通
Low
Output
SDRAM命令输入
CAS_N
列地址选通
Low
Output
SDRAM命令输入
WE_N
写使能
Low
Output
SDRAM命令输入
.DQ[DSIZE-1:
0]
数据总线
NA
I/O
SDRAM数据总线
DQM[(DSIZE/8)-1:
0]
数据屏蔽写
High
Output
SDRAM数据屏蔽,在数据写器件屏蔽单个字节数据
NA:
SDRAMControllerCommandInterface
TheSDRSDRAMControllerprovidesasynchronouscommandinterfacetotheSDRAMandseveralcontrolregisters.
Table3showsthecommands,whicharedescribedinfollowingsections.Thefollowingrulesapplytothecommands:
■Allcommands,exceptNOP,aredrivenbytheuserontoCMD[2:
0];ADDRandDATAINaresetappropriatelyfortherequestedcommand.Thecontrollerregistersthecommandonthenextrisingclockedge
■ToacknowledgethecommandthecontrollerassertsCMDACKforoneclockperiod
■ForREADAorWRITEAcommands,theusershouldstartreceivingorwritingdataonDATAOUTandDATAIN
■TheusermustdriveNOPontoCMD[2:
0]bythenextrisingclockedgeafterCMDACKisasserted
表3.接口命令
Command
Value
Description
NOP
000b
空操作
READA
001b
带自动预充电的SDRAM读操作
WRITEA
010b
带自动预充电的SDRAM写操作
REFRESH
011b
SDRAM自动刷新
PRECHARGE
100b
对SDRAM所有存储体预充电
LOAD_MODE
101b
SDRAM模式寄存器装入r.
LOAD_REG1
110b
装入控制器配置寄存器
LOAD_REG2
111b
装入控制器刷新周期寄存器
NOPCommand
NOPisanooperationcommandtothecontroller.WhenNOPisdetectedbythecontroller,itperformsaNOPinthefollowingclockcycle.ANOPmustbeissuedthefollowingclockcycleafterthecontrollerhasacknowledgedacommand.TheNOPcommandhasnoaffectonSDRAMaccessesthatarealreadyinprogress.
READACommand
TheREADAcommandinstructstheSDRSDRAMControllertoperformaburstreadwithauto-prechargetotheSDRAMatthememoryaddressspecifiedbyADDR.TheSDRSDRAMControllerissuesanACTIVATEcommandtotheSDRAMfollowedbyaREADAcommand.ThereadburstdatafirstappearsonDATAOUT(RCD+CL+2)aftertheSDRSDRAMControllerassertsCMDACK.DuringaREADAcommandtheusermustkeepDMlow.Whenthecontrollerisconfiguredforfull-pagemode,theREADAcommandbecomesREAD(READwithoutauto-precharge).Figure2showsanexampletimingdiagramforaREADAcommand.ThefollowingsequencedescribesthegeneraloperationoftheREADAcommand:
■TheuserassertsREADA,ADDRandDM
■TheSDRSDRAMControllerassertsCMDACKtoacknowledgethecommandandsimultaneouslystartsissuingcommandstotheSDRAMdevices
■OneclockafterCMDACKisasserted,theusermustassertNOP
■TheCMDACKpresentsthefirstreadburstvalueonDATAOUT,theremainderofthereadburstsfolloweveryclockcycle
WRITEACommand
TheWRITEAcommandinstructstheSDRSDRAMControllertoperformaburstwritewithauto-prechargetotheSDRAMatthememoryaddressspecifiedbyADDR.TheSDRSDRAMControllerwillissueanACTIVATEcommandtotheSDRAMfollowedbyaWRITEAcommand.ThefirstdatavalueintheburstsequencemustbepresentedwiththeWRITEAandADDRaddress.ThehostmuststartclockingdataalongwiththedesiredDMvaluesintotheSDRSDRAMController(tRCD–2)clocksaftertheSDRSDRAMControllerhasacknowledgedtheWRITEAcommand.SeeaSDRAMdatasheetforhowtousethedatamasklinesDM/DQM.WhentheSDRSDRAMControllerisinthefull-pagemodeWRITEAbecomesWRITE(writewithoutauto-precharge).Figure3showsanexampletimingdiagramforaWRITEAcommand.ThefollowingsequencedescribesthegeneraloperationofaWRITEAcommand:
■TheuserassertsWRITEA,ADDR,thefirstwritedatavalueonDATAIN,andthedesireddatamaskvalueonDM
■TheSDRSDRAMControllerassertsCMDACKtoacknowledgethecommandandsimultaneouslystartsissuingcommandstotheSDRAMdevices
■OneclockafterCMDACKwasasserted,theuserassertsNOPonCMD
■TheuserclocksdataanddatamaskvaluesintotheSDRSDRAMControllerthroughDATAINandDM
REFRESHCommand
TheREFRESHcommandinstructstheSDRSDRAMControllertoperformanARFcommandtotheSDRAM.TheSDRSDRAMControlleracknowledgestheREFRESHcommandwithCMDACK.Figure4showsanexampletimingdiagramoftheREFRESHcommand.ThefollowingsequencedescribesthegeneraloperationofaREFRESHcommand:
■TheuserassertsREFRESHontheCMDinput
■TheSDRSDRAMControllerassertsCMDACKtoacknowledgethecommandandsimultaneouslystartsissuingcommandstotheSDRAMdevices
■TheuserassertsNOPonCMD
PRECHARGECommand
ThePRECHARGEcommandinstructstheSDRSDRAMControllertoperformaPCHcommandtotheSDRAM.TheSDRSDRAMControlleracknowledgesthecommandwithCMDACK.ThePCHcommandisalsousedtogenerateaburststoptotheSDRAM.UsingPRECHARGEtoterminateaburstisonlysupportedinthefull-pagemode.
NotethattheSDRSDRAMControlleraddsalatencyfromwhenthehostissuesacommandtowhentheSDRAMseesthePRECHARGEcommandof4clocks.Ifafull-pagereadburstistobestoppedafter100cycles,thePRECHARGEcommandmustbeasserted(4+CL–1)clocksbeforethedesiredendoftheburst(CL–1requirementisimposedbytheSDRAMdevices).SoiftheCASlatencyis3,thePRECHARGEcommandmustbeissued(100–3–1–4)=92clocksintotheburst.
Figure5showsanexampletimingdiagramofthePRECHARGEcommand.ThefollowingsequencedescribesthegeneraloperationofaPRECHARGEcommand:
⏹TheuserassertsPRECHARGEonCMD
⏹TheSDRSDRAMControllerassertsCMDACKtoacknowledgethecommandandsimultaneouslystartsissuingcommandstotheSDRAMdevices
⏹TheuserassertsNOPonCMD
LOAD_MODE
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- SDRSDRAM 控制器 白皮书 中英文 对照 版本
![提示](https://static.bingdoc.com/images/bang_tan.gif)