For QuartusModelSim程序以及对应的testbench.docx
- 文档编号:10668570
- 上传时间:2023-05-27
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- 页数:21
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For QuartusModelSim程序以及对应的testbench.docx
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ForQuartusModelSim程序以及对应的testbench
通过查找“啊啊n”可以快速定位某一个程序
啊啊1###########空调温度控制器#####################
moduletemp_ctrl(clock,temp_high,temp_low,too_hot,too_cold,just_right,heat,cool);
inputclock;
inputtemp_high,temp_low;
outputtoo_hot,too_cold,just_right;
outputheat,cool;//对应加热和制冷两种操作
regheat,cool;
reg[2:
0]state;//共有三种状态通过0位1位2位的值为1来区别
assigntoo_hot=state[0];//assign是分配的意思
assigntoo_cold=state[1];
assignjust_right=state[2];//
parameter
HOT=3'b0_0_1,//对应state[0]第0位值为1
COLD=3'b0_1_0,
OK=3'b1_0_0;
always@(posedgeclock)
begin
case(state)//case(*)--default--endcase
OK:
//一种状态可能向另外两种转变if()beginend和elseif()beginend然后“else;”
if(temp_high==1&&temp_low==0)
begin
state<=HOT;
heat<=0;
cool<=1;
end
elseif(temp_high==0&&temp_low==1)
begin
state<=COLD;
heat<=1;
cool<=0;
end
else;
HOT:
if(temp_high==0&&temp_low==1)
begin
state<=COLD;
heat<=1;
cool<=0;
end
elseif(temp_high==0&&temp_low==0)
begin
state<=OK;
heat<=0;
cool<=0;
end
else;
COLD:
if(temp_high==1&&temp_low==0)
begin
state<=HOT;
heat<=0;
cool<=1;
end
elseif(temp_high==0&&temp_low==0)
begin
state<=OK;
heat<=0;
cool<=0;
end
else;
default:
;
endcase
end
initial//用于定义初始状态
begin
state<=OK;
heat<=0;
cool<=0;
end
endmodule
######################################
对应的testbench程序//其实很短
moduletest
regclk;
reghigh,low;
wirehot,cold,ok;
wireheat,cool;
parameterDELAY=100;
temp_ctrlm(clk,high,low,hot,cold,ok,heat,cool);//例化。
源文件中的实体名U(对应的参数);
always#(DELAY/2)clk=~clk;//一个简单的语句解决了时钟的问题
initial//定义初始的状态
begin
clk=0;
high=0;
low=0;
end
always
begin
#DELAYhigh={$random}%2;//$random==createarandomnumber
#DELAYlow={$random}%2;
end
initial
$monitor($time,,,"clk=%dhigh=%dlow=%dheat=%dcool=%d",clk,high,low,heat,cool);
endmodule
#################################
啊啊2半加器
##################################
modulehalfadder(A,B,CO,S);
inputA,B;
outputCO,S;
wireCO,S;
assignS=A^B;
assignCO=A&B;
endmodule
###############
modulehalfadder_tst;
rega,b;
wireco,s;
halfadderu1(.A(a),.B(b),.CO(co),.S(s));
initial
begin
a=1;
b=1;
#10begina=1;b=1;end
#10begina=1;b=0;end
#10begina=0;b=1;end
#10begina=0;b=0;end
#10$stop;
end
endmodule
#############################
啊啊3交通信号灯
libraryIEEE;
useIEEE.std_logic_1164.all;
entitytrafficis
port(clk,timed,car:
instd_logic;
start_timer,major_green,minor_green:
outstd_logic);
endentitytraffic;
architectureasmlaoftrafficis
begin
processis
typestate_typeis(G,R);
variablestate:
state_type;
begin
start_timer<='0';
waituntilclk='1';
casestateis
whenG=>
major_green<='1';
minor_green<='0';
if(car='1')then
start_timer<='1';
waitfor1us;
start_timer<='0';
state:
=R;
endif;
whenR=>
major_green<='0';
minor_green<='1';
if(timed='1')then
state:
=G;
endif;
endcase;
endprocess;
endarchitectureasmla;
####################
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYtraffic_vhd_tstIS
ENDtraffic_vhd_tst;
ARCHITECTUREtraffic_archOFtraffic_vhd_tstIS
--constants
--signals
SIGNALcar:
STD_LOGIC;
SIGNALclk:
STD_LOGIC;
SIGNALmajor_green:
STD_LOGIC;
SIGNALminor_green:
STD_LOGIC;
SIGNALstart_timer:
STD_LOGIC;
SIGNALtimed:
STD_LOGIC;
COMPONENTtraffic
PORT(
car:
INSTD_LOGIC;
clk:
INSTD_LOGIC;
major_green:
OUTSTD_LOGIC;
minor_green:
OUTSTD_LOGIC;
start_timer:
OUTSTD_LOGIC;
timed:
INSTD_LOGIC
);
ENDCOMPONENT;
BEGIN
i1:
traffic
PORTMAP(
--listconnectionsbetweenmasterportsandsignals
car=>car,
clk=>clk,
major_green=>major_green,
minor_green=>minor_green,
start_timer=>start_timer,
timed=>timed
);
init:
PROCESS
--variabledeclarations
BEGIN
car<='0';
timed<='0';
waitfor1us;
car<='1';
waitfor1.5us;
car<='0';
waitfor4us;
timed<='1';
waitfor1us;
timed<='0';
--codethatexecutesonlyonce
WAIT;
ENDPROCESSinit;
clk_gen:
process
begin
clk<='1';
waitfor0.2us;
clk<='0';
waitfor0.2us;
endprocess;
ENDtraffic_arch;
#########################
啊啊47段数码管
libraryIEEE;
useIEEE.std_logic_1164.all;
entitysegis
port(a:
instd_logic_vector(3downto0);
z:
outstd_logic_vector(6downto0));
endentityseg;
architectureaaofsegis
begin
withaselect
z<="1110111"when"0000",
"0010010"when"0001",
"1011101"when"0010",
"1011011"when"0011",
"0111010"when"0100",
"1101011"when"0101",
"1101111"when"0110",
"1010010"when"0111",
"1111111"when"1000",
"1111011"when"1001",
"1101101"when"1010"|"1011"|"1100"|"1101"|"1110"|"1111",
"0000000"whenothers;
endarchitectureaa;
#########################
对应的testbench如下(采用插入模板,只需看):
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYseg_vhd_tstIS
ENDseg_vhd_tst;
ARCHITECTUREseg_archOFseg_vhd_tstIS
--constants
--signals
SIGNALa:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALz:
STD_LOGIC_VECTOR(6DOWNTO0);
COMPONENTseg
PORT(
a:
INSTD_LOGIC_VECTOR(3DOWNTO0);
z:
OUTSTD_LOGIC_VECTOR(6DOWNTO0)
);
ENDCOMPONENT;
BEGIN
i1:
seg
PORTMAP(
--listconnectionsbetweenmasterportsandsignals
a=>a,
z=>z
);
init:
PROCESS
--variabledeclarations
BEGIN
//从这里开始,其他EDA工具自己生成的模板,真正自己写的就这一部分waitfor10ns;
a<="0000";
waitfor10ns;
a<="0001";
waitfor10ns;
a<="0010";
waitfor10ns;
a<="0011";
waitfor10ns;
a<="0100";
waitfor10ns;
a<="0101";
waitfor10ns;
a<="0110";
waitfor10ns;
a<="0111";
waitfor10ns;
a<="1000";
waitfor10ns;
a<="1001";
waitfor10ns;
a<="1010";
waitfor10ns;
a<="1011";
waitfor10ns;
a<="1100";
waitfor10ns;
a<="1101";
waitfor10ns;
a<="1110";
waitfor10ns;
a<="1111";
//从这里结束,其他EDA工具自己生成的模板,真正自己写的就这一部分
--codethatexecutesonlyonce
WAIT;
ENDPROCESSinit;
ENDseg_arch;
#############################
啊啊5自动售货机
libraryIEEE;
useIEEE.std_logic_1164.all;
entityvendingis
port(clk,reset,twenty,ten:
instd_logic;
ready,dispense,ret,coin:
outstd_logic);
endentityvending;
architectureasmofvendingis
typestate_typeis(A,B,C,D,F,I);
signalpresent_state,next_state:
state_type;
begin
seq:
process(clk,reset)is
begin
if(reset='1')then
present_state<=A;
elsif(rising_edge(clk))then
present_state<=next_state;
endif;
endprocessseq;
com:
process(twenty,ten,present_state)is
begin
ready<='0';
dispense<='0';
ret<='0';
coin<='0';
casepresent_stateis
whenA=>
ready<='1';
if(twenty='1')then
next_state<=D;
elsif(ten='1')then
next_state<=A;
endif;
whenB=>
dispense<='1';
next_state<=A;
whenC=>
coin<='1';
if(twenty='1')then
next_state<=F;
elsif(ten='1')then
next_state<=D;
else
next_state<=C;
endif;
whenD=>
coin<='1';
if(twenty='1')then
next_state<=B;
elsif(ten='1')then
next_state<=F;
else
next_state<=D;
endif;
whenF=>
coin<='1';
if(twenty='1')then
next_state<=I;
elsif(ten='1')then
next_state<=B;
else
next_state<=F;
endif;
whenI=>
ret<='1';
next_state<=A;
endcase;
endprocesscom;
endarchitectureasm;
#################################3
对应的testbench
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYvending_vhd_tstIS
ENDvending_vhd_tst;
ARCHITECTUREvending_archOFvending_vhd_tstIS
--constants
--signals
SIGNALclk:
STD_LOGIC;
SIGNALcoin:
STD_LOGIC;
SIGNALdispense:
STD_LOGIC;
SIGNALready:
STD_LOGIC;
SIGNALreset:
STD_LOGIC;
SIGNALret:
STD_LOGIC;
SIGNALten:
STD_LOGIC;
SIGNALtwenty:
STD_LOGIC;
COMPONENTvending
PORT(
clk:
INSTD_LOGIC;
coin:
OUTSTD_LOGIC;
dispense:
OUTSTD_LOGIC;
ready:
OUTSTD_LOGIC;
reset:
INSTD_LOGIC;
ret:
OUTSTD_LOGIC;
ten:
INSTD_LOGIC;
twenty:
INSTD_LOGIC
);
ENDCOMPONENT;
BEGIN
i1:
vending
PORTMAP(
--listconnectionsbetweenmasterportsandsignals
clk=>clk,
coin=>coin,
dispense=>dispense,
ready=>ready,
reset=>reset,
ret=>ret,
ten=>ten,
twenty=>twenty
);
clk_gen:
process
begin
clk<='1';
waitfor50ns;
clk<='0';
waitfor50ns;
endprocess;
init:
PROCESS
--variabledeclarations
BEGIN
reset<='1';
twenty<='0';
ten<='0';
waitfor100ns;
reset<='0';
waitfor100ns;
ten<='1';
waitfor100ns;
ten<='0';
waitfor200ns;
twenty<='1';
waitfor100ns;
twenty<='0';
waitfor200ns;
ten<='1';
waitfor100ns;
ten<='0';
waitfor500ns;
ten<='1';
waitfor100ns;
ten<='0';
waitfor250ns;
twenty<='1';
waitfor100ns;
twenty<='0';
waitfor250ns;
twenty<='1';
waitfor100ns;
twenty<='0';
--codethatexecutesonlyonce
WAIT;
ENDPROCESSinit;
ENDvending_arch;
#######################################3
啊啊6简单分频器
libraryIEEE;
useIEEE.std_logic_1164.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
entityclkdivis
port(clk:
instd_logic;
clk_8hz:
outstd_logic;
clk_2hz:
outstd_logic);
endentityclkdiv;
architecturebehaveofclkdivis
signalcnt:
std_logic_vector(7downto0):
="00000001";
begin
process(clk)
begin
ifclk'eventandclk='1'then
cnt<=cnt+1;
clk_8hz<=cnt
(1);/
clk_2hz<=cnt(4);
endif;
endprocess;
endarchitecturebehave;
################1
对应的testbench
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYclkdiv_vhd_tstIS
ENDclkdiv_vhd_tst;
ARCHITECTUREclkdiv_archOFclkdiv_vhd_tstIS
--constants
--signals
SIGNALclk:
STD_LOGIC;
SIGNALclk_2hz:
STD_LOGIC;
SIGNALclk_8hz:
STD_LOGIC;
COMPONENTclkdiv
PORT(
clk:
INSTD_LOGIC;
clk_2hz:
OUTSTD_LOGIC;
clk_8hz:
OUTSTD_LOGIC
);
ENDCOMPONENT;
BEGIN
i1:
clkdiv
PORTMAP(
--listconnectionsbetweenmasterportsandsignals
clk=>clk,
clk_2hz=>clk_2hz,
clk_8hz=>clk_8hz
);
clk_gen:
process
begin
clk<='1';
waitfor50ns;
c
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