EDA重要程序图万能无敌版.docx
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EDA重要程序图万能无敌版.docx
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EDA重要程序图万能无敌版
图3-18
程序设计:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYqudongIS
PORT
(clk:
inSTD_LOGIC;
enable:
instd_logic;
data:
INintegerRANGE0TO5;
segout:
outSTD_LOGIC_VECTOR(6downto0));
END;
ARCHITECTUREbehaviorOFqudongIS
BEGIN
process(Clk,data)
BEGIN
IFfalling_edge(Clk)andenable='1'then
casedatais
when0=>segout<="0111111";
when1=>segout<="0000110";
when2=>segout<="1011011";
when3=>segout<="1001111";
when4=>segout<="1100110";
when5=>segout<="1101101";
when6=>segout<="1111101";
when7=>segout<="0000111";
when8=>segout<="1111111";
when9=>segout<="1101111";
whenothers=>null;
ENDCASE;
ENDIF;
ENDPROCESS;
END;
3.3.7数码管驱动的设计——黄灯驱动
由于黄灯固定时间是5秒,因此变化范围是0至5秒,七段数码管
只要能显示0-5的数就行了,所以单独用一个数码管驱动。
图3-19图3-20
程序设计:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYHDqudongISPORT
(clk:
inSTD_LOGIC;
enable:
instd_logic;
data:
INintegerRANGE0TO5;
segout:
outSTD_LOGIC_VECTOR(6downto0));
END;
ARCHITECTUREbehaviorOFHDqudongIS
BEGIN
process(Clk,data)
BEGIN
IFfalling_edge(Clk)andenable='1'then
casedatais
when0=>segout<="0111111";
when1=>segout<="0000110";
when2=>segout<="1011011";
when3=>segout<="1001111";
when4=>segout<="1100110";
when5=>segout<="1101101";
whenothers=>null;
ENDCASE;
ENDIF;
ENDPROCESS;
END;
4.顶层连接及其仿真
4.1顶层文件的设计
Libraryieee;
Useieee.std_logic_1164.all;
Useieee.std_logic_unsigned.all;
Useieee.std_logic_arith.all;
Entityljiaotongdengis
Port
(clka:
instd_logic;
Reset:
instd_logic;
hold:
instd_logic;
reda,greena,yellowa:
outstd_logic;
redb,greenb,yellowb:
outstd_logic;
displaya,displayb,displayc,displayd:
outstd_logic_vector(0to6));
end;
architecturecontrolofljiaotongdengis
signalcountnum:
integerrange0to50;
Signalclk:
std_logic;
Signalnuma,numb,numc,numd:
integerrange0to9;
signalnoa,nob:
integerrange0to25;
SignalQina,qinb,qinc,qind:
std_logic_vector(3downto0);
signalclock:
std_logic;
signalclock1:
std_logic;
signaltout:
integerrange0to499;
begin
Process(clka)
begin
Ifrising_edge(clka)then
Iftout=999then
Tout<=0;
clock1<=notclock1;
Elsetout<=tout+1;
Endif;
endif;
clk<=clock1;
Endprocess;
process(clk)
begin
ifreset='1'then
countnum<=0;
elsifrising_edge(clk)then
ifcountnum=499then
countnum<=0;
else
countnum<=countnum+1;
endif;
endif;
endprocess;
process(clka)
begin
ifrising_edge(clk)then
ifhold='1'then
reda<='1';
redb<='1';
greena<='0';
greenb<='0';
else
ifcountnum<=19then
noa<=20-countnum;
reda<='0';
greena<='1';
elsif(countnum<=24)then
noa<=25-countnum;
reda<='0';
greena<='0';
else
noa<=50-countnum;
reda<='1';
greena<='0';
endif;
ifcountnum<=24then
nob<=25-countnum;
redb<='1';
greenb<='0';
elsifcountnum<=44then
nob<=45-countnum;
redb<='0';
greenb<='1';
else
nob<=50-countnum;
redb<='0';
greenb<='0';
endif;
endif;
endif;
endprocess;
process(clk)
begin
ifhold='0'then
if(countnum>20andcountnum<=25)then
yellowa<=clk;
yellowb<='0';
elsif(countnum>45andcountnum<=50)then
yellowa<='0';
yellowb<=clk;
else
yellowa<='0';
yellowb<='0';
endif;
endif;
endprocess;
Process(clka)
Begin
Ifrising_edge(clka)then
Ifnoa>=20then
numa<=2;
numb<=noa-20;
Elsifnoa>=10then
Numa<=1;
numb<=noa-10;
Else
Numa<=0;
Numb<=noa;
Endif;
Endif;
Endprocess;
Process(clka)
Begin
Ifrising_edge(clka)then
Ifnob>=20then
numc<=2;
numd<=nob-20;
Elsifnob>=10then
Numc<=1;
numd<=nob-10;
Else
Numc<=0;
Numd<=nob;
Endif;
endif;
Endprocess;
process(clka)
begin
Qina<=conv_std_logic_vector(numa,4);
Qinb<=conv_std_logic_vector(numb,4);
Qinc<=conv_std_logic_vector(numc,4);
Qind<=conv_std_logic_vector(numd,4);
Caseqinais
When"0000"=>displaya<="1111110";
When"0001"=>displaya<="0110000";
When"0010"=>displaya<="1101101";
When"0011"=>displaya<="1111001";
When"0100"=>displaya<="0110011";
When"0101"=>displaya<="1011011";
When"0110"=>displaya<="1011111";
When"0111"=>displaya<="1110000";
When"1000"=>displaya<="1111111";
When"1001"=>displaya<="1111011";
Whenothers=>displaya<="0000000";
endcase;
Caseqinbis
When"0000"=>displayb<="1111110";
When"0001"=>displayb<="0110000";
When"0010"=>displayb<="1101101";
When"0011"=>displayb<="1111001";
When"0100"=>displayb<="0110011";
When"0101"=>displayb<="1011011";
When"0110"=>displayb<="1011111";
When"0111"=>displayb<="1110000";
When"1000"=>displayb<="1111111";
When"1001"=>displayb<="1111011";
Whenothers=>displayb<="0000000";
endcase;
Caseqincis
When"0000"=>displayc<="1111110";
When"0001"=>displayc<="0110000";
When"0010"=>displayc<="1101101";
When"0011"=>displayc<="1111001";
When"0100"=>displayc<="0110011";
When"0101"=>displayc<="1011011";
When"0110"=>displayc<="1011111";
When"0111"=>displayc<="1110000";
When"1000"=>displayc<="1111111";
When"1001"=>displayc<="1111011";
Whenothers=>displayc<="0000000";
endcase;
Caseqindis
When"0000"=>displayd<="1111110";
When"0001"=>displayd<="0110000";
When"0010"=>displayd<="1101101";
When"0011"=>displayd<="1111001";
When"0100"=>displayd<="0110011";
When"0101"=>displayd<="1011011";
When"0110"=>displayd<="1011111";
When"0111"=>displayd<="1110000";
When"1000"=>displayd<="1111111";
When"1001"=>displayd<="1111011";
Whenothers=>displayd<="0000000";
Endcase;
Endprocess;
End;
4.2整体仿真波形
图4-1仿真波形
图4-2总体电路图
5.心得体会
通过此次课程设计,使我对EDA程序设计有了进一步的学习,进一步的认识;在程序的设计,程序的调试方面都学到了很多东西,现在能够熟练的使用QuartsII,能够用VHDL语言编写简单的、实用的小程序,这次EDA课程设计重点学习了交通灯控制电路程序的编写、仿真、还有硬件下载、操作等过程。
在这期间查阅了大量的关于EDA的资料,特别是在网上和图书馆我找到了大量的关于VHDL编程的资料。
此外,在整个过程中我认为调试程序是很重要的,要有耐心和探索研究的能力。
我在第一次编译时有三十几个错误,其中有输入错误、语法错误,如:
工程名和实体名不一致,少了分号或者少了ENDIF或者忘加了一个分号等错误。
发现错误之后就要一遍一遍的仔细查错,直到没有错误,然后可以进行波行仿真了。
通过这次的设计,进一步了解了EDA技术,收获很大,对软件编程、排错调试、相关仪器设备的使用技能等方面得到较全面的锻炼和提高。
参考文献:
潘松,黄继业.《EDA技术实用教程》.科学出版社.2006.9
李辉.《PLD与数字系统设计》.西安电子科技大学出版社.2005
蒋璇.臧蠢华.《数字系统设计与PLD应用》(第二版).电子工业出版社.2005
曾繁泰等.《VHDL 程序设计》(第二版).清华大学出版社
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