湖南大学数电课程设计.docx
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湖南大学数电课程设计.docx
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湖南大学数电课程设计
数电课程设计实验报告
课题:
竞赛抢答器
学院:
电气与信息工程学院
姓名:
班级:
电子信息工程1001班
一、课程设计的要求及目的
1.了解电子设计的具体流程和方法。
2.掌握电子设计的基本要求,能够运用所学的知识解决生活中的一些问题。
3.初步掌握VHDL语言编程,并设计出一个有意义的小型系统。
4.掌握AltiumDesigner6.9软件的应用,并且了解相关硬件的组成和功能。
5.用EDA(ElectronicDesignAutomation)或者原理图完成一个课题的设计,并达到相应的功能要求。
二、设计的功能要求
在许多比赛活动中,为了准确、公正、直观地判断出第一抢答者,通常设置一台抢答器,通过数显、灯光及音响等各种手段批示出第一抢答者。
同时,还可以设置计分、犯规及奖惩记录等各种功能。
本设计利用EDA技术,可容纳8组参赛,每组设置一个按钮供参赛者抢答使用。
主持人按下开始按键后,10s倒计时开始,当一组抢答器按下后,1602LCD显示抢答的组别。
由于抢答器具有第一信号鉴别和锁存功能使其余的组就抢答无效,抢答的组回答问题后由主持人进行加减分,然后主持人按复位键后继续进行抢答。
1、在1602LCD屏幕上显示所需组别及分数;
2、考虑到有选手犯规,在主持人未按下开始键但是已经有组别按下抢答键时会在屏幕显示该组别犯规(FG),并由主持人手动减分;
3、按下开始键后,有10s的时间供选手们抢答,如果30s后仍无人抢答,则蜂鸣器报警,并在屏幕上显示超时(CS);
4、每个组别设置的初始分数为0分,加分上限为9分;
5、能实现系统手动复位,复位后回到初始状态,并等待主持人按下开始键。
三、设计思路框图
四、VHDL程序
1、键盘转按键模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
entityPADTOKEYis
port(
CPIN,R,VALIDKEY:
INSTD_LOGIC;
KEY:
INSTD_LOGIC_VECTOR(3DOWNTO0);
KEYOUT:
OUTSTD_LOGIC_VECTOR(15DOWNTO0);
CLK_1MHZ,RST:
OUTSTD_LOGIC
);
endentity;
architectureJGTofPADTOKEYis
SIGNALCTCP:
INTEGERRANGE0TO5;
SIGNALCPO:
STD_LOGIC:
='0';
SIGNALCTCPO:
INTEGERRANGE0TO4999;
TYPESTATESIS(S0,S1,S2);
SIGNALS:
STATES;
begin
PROCESS(CPIN)
BEGIN
IFCPIN='1'ANDCPIN'EVENTTHEN
IFCTCP=5THEN
CPO<=NOTCPO;CTCP<=0;
ELSE
CTCP<=CTCP+1;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CPO,R)
BEGIN
CLK_1MHZ<=CPO;
IFR='1'THEN
RST<='0';S<=S0;CTCPO<=0;KEYOUT<="0000000000000000";
ELSIFCPO='1'ANDCPO'EVENTTHEN
IFCTCPO/=4999THEN
CTCPO<=CTCPO+1;
ELSE
CTCPO<=0;
CASESIS
WHENS0=>RST<='0';
IFVALIDKEY='1'THEN
S<=S1;
CASEKEYIS
WHEN"0000"=>KEYOUT<="0000000000000001";
WHEN"0001"=>KEYOUT<="0000000000000010";
WHEN"0010"=>KEYOUT<="0000000000000100";
WHEN"0011"=>KEYOUT<="0000000000001000";
WHEN"0100"=>KEYOUT<="0000000000010000";
WHEN"0101"=>KEYOUT<="0000000000100000";
WHEN"0110"=>KEYOUT<="0000000001000000";
WHEN"0111"=>KEYOUT<="0000000010000000";
WHEN"1000"=>KEYOUT<="0000000100000000";
WHEN"1001"=>KEYOUT<="0000001000000000";
WHEN"1010"=>KEYOUT<="0000010000000000";
WHEN"1011"=>KEYOUT<="0000100000000000";
WHEN"1100"=>KEYOUT<="0001000000000000";
WHEN"1101"=>KEYOUT<="0010000000000000";
WHEN"1110"=>KEYOUT<="0100000000000000";
WHEN"1111"=>KEYOUT<="1000000000000000";
WHENOTHERS=>NULL;
ENDCASE;
ELSE
S<=S0;KEYOUT<="0000000000000000";
ENDIF;
WHENS1=>RST<='1';S<=S2;
WHENS2=>RST<='0';S<=S0;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDIF;
ENDPROCESS;
endarchitectureJGT;
此模块使用状态机将键盘的16个按键转换为16个按键信号。
2、显示模块
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
entityQDQLCDis
port(CPIN,R,BUSY:
INSTD_LOGIC;
FS1,FS2,FS3,FS4,FS5,FS6,FS7,FS8,TM:
INSTD_LOGIC_VECTOR(7DOWNTO0);
ZB:
INSTD_LOGIC_VECTOR(3DOWNTO0);
TESHU:
INSTD_LOGIC_VECTOR(1DOWNTO0);
CLK,RST,STROBE,OUTLINE:
OUTSTD_LOGIC;
DATA:
OUTSTD_LOGIC_VECTOR(7DOWNTO0);
ADDR:
OUTSTD_LOGIC_VECTOR(3DOWNTO0)
);
endentity;
architectureJGTofQDQLCDis
TYPESTATESIS(S0,S1,S2,S3,S4);
SIGNALS:
STATES;
SIGNALLCDPT:
INTEGERRANGE0TO27;
SIGNALCPCT:
INTEGERRANGE0TO65535;
SIGNALCP:
STD_LOGIC;
--SIGNALASCEW,ASCSN:
STD_LOGIC_VECTOR(7DOWNTO0);
begin
PROCESS(CPIN,R)
BEGIN
CLK<=CPIN;
IFR='1'THEN
CPCT<=65535;
ELSIFCPIN='1'ANDCPIN'EVENTTHEN
IFCPCT=0THEN
CPCT<=65535;CP<=NOTCP;
ELSE
CPCT<=CPCT-1;
ENDIF;
ENDIF;
ENDPROCESS;--·ÖƵΪ500USÖÜÆÚ
--Ö÷½ø³Ì£ºÄâ²ÉÓÃ500usʱÖÓ£¬¼´ÔÚ500usºóÍê³É״̬ת»»£¬ÐÞ¸ÄLCDPTÖ¸Õë
--S0:
³õʼ״̬,ÔÚR=1ʱ£¬´¦ÓÚS0״̬,LCDPT=0
--Á÷³Ì£ºÊä³örst=1,תS1
--S1:
Êä³öRST=0;ÅжÏBUSY=0?
:
Y:
LCDPT+1;LCDPTµ½¹Ì¶¨×îºó£¿:
:
N:
->S2
--:
:
Y:
תS3
--;N;NULL
--S2:
¸ø³öSTROBEÐźš£×ªS1
--S1,S2Íê³É³õʼ»¯¹Ì¶¨ÏÔʾµÄ¹¦ÄÜ
PROCESS(CP,R)
BEGIN
IFR='1'THEN
S<=S0;LCDPT<=0;RST<='1';
ELSIFCP='1'ANDCP'EVENTTHEN
CASESIS
WHENS0=>S<=S1;LCDPT<=0;RST<='1';
WHENS1=>RST<='0';STROBE<='0';
IFBUSY='0'THEN
LCDPT<=LCDPT+1;
IFLCDPT=7THEN
S<=S3;
ELSE
S<=S2;
ENDIF;
ENDIF;
WHENS2=>S<=S1;STROBE<='1';
--S3~S4Íê³ÉɨÃèÏÔʾ¹¦ÄÜ
--S3:
BUSY=0?
:
Y:
LCDPTÑ»·+1£¬×ªS4
--S4:
¸ø³öSTROBEÐźţ¬×ªS3
WHENS3=>STROBE<='0';
IFBUSY='0'THEN
IFLCDPT=27THEN
LCDPT<=7;
ELSE
LCDPT<=LCDPT+1;
ENDIF;
S<=S4;
ENDIF;
WHENS4=>STROBE<='1';S<=S3;
WHENOTHERS=>NULL;
ENDCASE;
ENDIF;
ENDPROCESS;
--Ñ¡ÔñÊä³ö½ø³Ì(LCDPT)
--LCDPT=0,NULL
--=1~6ÏÔʾZB:
TM:
E45H,5W57H,6S53H,9N4EH,10
PROCESS(LCDPT)
BEGIN
CASELCDPTIS
WHEN0=>NULL;
WHEN1=>DATA<="01011010";ADDR<="1001";OUTLINE<='1';--Z
WHEN2=>DATA<="01000010";ADDR<="1010";OUTLINE<='1';--B
WHEN3=>DATA<="00111010";ADDR<="0100";OUTLINE<='1';--:
WHEN4=>DATA<="01010100";ADDR<="0010";OUTLINE<='1';--T
WHEN5=>DATA<="01001101";ADDR<="0011";OUTLINE<='1';--M
WHEN6=>DATA<="00111010";ADDR<="1011";OUTLINE<='1';--:
--LCDPT=7~22ÏÔʾFS1~FS8
--LCDPT=23~25ÏÔʾZB/TM
WHEN7=>DATA<="0011"&FS1(7DOWNTO4);ADDR<="0000";OUTLINE<='0';
WHEN8=>DATA<="0011"&FS1(3DOWNTO0);ADDR<="0001";OUTLINE<='0';
WHEN9=>DATA<="0011"&FS2(7DOWNTO4);ADDR<="0010";OUTLINE<='0';
WHEN10=>DATA<="0011"&FS2(3DOWNTO0);ADDR<="0011";OUTLINE<='0';
WHEN11=>DATA<="0011"&FS3(7DOWNTO4);ADDR<="0100";OUTLINE<='0';
WHEN12=>DATA<="0011"&FS3(3DOWNTO0);ADDR<="0101";OUTLINE<='0';
WHEN13=>DATA<="0011"&FS4(7DOWNTO4);ADDR<="0110";OUTLINE<='0';
WHEN14=>DATA<="0011"&FS4(3DOWNTO0);ADDR<="0111";OUTLINE<='0';
WHEN15=>DATA<="0011"&FS5(7DOWNTO4);ADDR<="1000";OUTLINE<='0';
WHEN16=>DATA<="0011"&FS5(3DOWNTO0);ADDR<="1001";OUTLINE<='0';
WHEN17=>DATA<="0011"&FS6(7DOWNTO4);ADDR<="1010";OUTLINE<='0';
WHEN18=>DATA<="0011"&FS6(3DOWNTO0);ADDR<="1011";OUTLINE<='0';
WHEN19=>DATA<="0011"&FS7(7DOWNTO4);ADDR<="1100";OUTLINE<='0';
WHEN20=>DATA<="0011"&FS7(3DOWNTO0);ADDR<="1101";OUTLINE<='0';
WHEN21=>DATA<="0011"&FS8(7DOWNTO4);ADDR<="1110";OUTLINE<='0';
WHEN22=>DATA<="0011"&FS8(3DOWNTO0);ADDR<="1111";OUTLINE<='0';
WHEN23=>DATA<="0011"&TM(7DOWNTO4);ADDR<="0101";OUTLINE<='1';
WHEN24=>DATA<="0011"&TM(3DOWNTO0);ADDR<="0110";OUTLINE<='1';
WHEN25=>DATA<="0011"&ZB(3DOWNTO0);ADDR<="1101";OUTLINE<='1';
WHEN26=>CASETESHUIS
WHEN"01"=>DATA<="01000110";ADDR<="1110";OUTLINE<='1';--F
WHEN"10"=>DATA<="01000011";ADDR<="1110";OUTLINE<='1';--C
WHENOTHERS=>NULL;
ENDCASE;
WHEN27=>CASETESHUIS
WHEN"01"=>DATA<="01000111";ADDR<="1111";OUTLINE<='1';--G
WHEN"10"=>DATA<="01010011";ADDR<="1111";OUTLINE<='1';--S
WHENOTHERS=>NULL;
ENDCASE;
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
endarchitectureJGT;
此模块采用状态机的方法在LCD上按格式显示抢答器的8个2位BCD码分数、抢答的组别、时间。
3、主模块
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
----Uncommentthefollowinglibrarydeclarationifinstantiating
----anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityqdmain1is
Port(TESHU:
outSTD_LOGIC_VECTOR(1downto0);
CPIN:
inSTD_LOGIC;
KEYOUT:
inSTD_LOGIC_VECTOR(15downto0);
R:
inSTD_LOGIC;
FS1:
outSTD_LOGIC_VECTOR(7downto0);
FS2:
outSTD_LOGIC_VECTOR(7downto0);
FS3:
outSTD_LOGIC_VECTOR(7downto0);
FS4:
outSTD_LOGIC_VECTOR(7downto0);
FS5:
outSTD_LOGIC_VECTOR(7downto0);
FS6:
outSTD_LOGIC_VECTOR(7downto0);
FS7:
outSTD_LOGIC_VECTOR(7downto0);
FS8:
outSTD_LOGIC_VECTOR(7downto0);
TM:
outSTD_LOGIC_VECTOR(7downto0);
ZB:
outSTD_LOGIC_VECTOR(3downto0));
endqdmain1;
architectureBehavioralofqdmain1is
SIGNALKSKEY:
STD_LOGIC:
='0';
SIGNALYIDA:
STD_LOGIC:
='0';
SIGNALJIAFLAG,JIANFLAG:
STD_LOGIC;
SIGNALCPCT:
INTEGERRANGE0TO4999;
SIGNALCP:
STD_LOGIC;
SIGNALCP1S:
INTEGERRANGE0TO999;
SIGNALCPCNT:
STD_LOGIC;
SIGNALTM1:
STD_LOGIC_VECTOR(7downto0);
SIGNALZB1:
STD_LOGIC_VECTOR(3downto0);
--SIGNALF1,F2,F3,F4,F5,F6,F7,F8:
STD_LOGIC_VECTOR(7downto0);
SIGNALFk1,Fk2,Fk3,Fk4,Fk5,Fk6,Fk7,Fk8:
STD_LOGIC_VECTOR(7downto0);
begin
TM<=TM1;
ZB<=ZB1;
FS1<=Fk1;FS2<=Fk2;FS3<=Fk3;FS4<=Fk4;FS5<=Fk5;FS6<=Fk6;FS7<=Fk7;FS8<=Fk8;
process(R,CPIN)
BEGIN
IFR='1'THEN
CPCT<=4999;
ELSIFCPIN='1'ANDCPIN'EVENTTHEN--20MHZ
IFCPCT=0THEN--cpshi500us;
CPCT<=4999;CP<=NOTCP;
ELSE
CPCT<=CPCT-1;
ENDIF;
ENDIF;
ENDPROCESS;
process(R,CP)
begin
IFR='1'THEN
CP1S<=0;
ELSIFCP='1'ANDCP'EVENTTHEN
IFCP1S=999THEN
CP1S<=0;
CPCNT<=NOTCPCNT;--CPCNTshi1s;
ELSE
CP1S<=CP1S+1;
ENDIF;
ENDIF;
endprocess;
process(CPIN,CPCNT)
begin
IFCPIN='1'ANDCPIN'EVENTTHEN
IFKEYOUT="1000000000000000"THEN
Fk1<="00000000";Fk2<="00000000";Fk3<="00000000";Fk4<="00000000";
Fk5<="00000000";Fk6<="00000000";Fk7<="00000000";Fk8<="00000000";
ELSIFR='1'THEN
YIDA<='0';
KSKEY<='0';
TM1<="00001001";
ZB1<="0000";
TESHU<="00";
JIAFLAG<='1';
JIANFLAG<='1';
ELSEIFYIDA='0'THEN
CASEKEYOUTIS
WHEN"0100000000000000"=>KSKEY<='1';--0SHIKAISHIJIAN
WHEN"0000000000000001"=>YIDA<='1';ZB1<="0001";--Fk1<=Fk1+1;
WHEN"0000000000000010"=>YIDA<='1';ZB1<="0010";--Fk2<="00000011";
WHEN"0000000000000100"=>YIDA<='1';ZB1<="0011";--Fk3<="00000011";
WHEN"0000000000010000"=>YIDA<='1';ZB1<="0100";--Fk4<="00000011";
WHEN"0000000000100000"=>YIDA<='1';ZB1<="0101";--Fk5<="00000011";
WHEN"0000000001000000"=>YIDA<='1';ZB1<="0110";--Fk6<="00000011";
WHEN"0000000100000000"=>YIDA<='1';ZB1<="0111";--Fk7<="00000011";
WHEN"0000001000000000"=>YIDA<='1';ZB1<="1000";--Fk8<="00000011";
--WHEN"0000001000000000"=>YIDA<='0';KSKEY<='0';--9qinglingjian
WHENOTHERS=>NULL;
ENDCASE;
IFKSKEY='1'THEN
IFCPCNT='1'ANDCPCNT'EVENTTHEN
IFTM1/="00000000"THEN
TM1<=TM1-1;
ENDIF;
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