锁相技术译文翻译.docx
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锁相技术译文翻译.docx
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锁相技术译文翻译
锁相技术译文翻译
英文原名:
PLLFrequencySynthesizerwithanAuxiliaryProgrammableDivider
译文:
具有辅助可编程分频器的锁相环频率合成器______
年级专业:
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2011年5月2日
英文
中文
AbstractThelock-uptimeofaPLLfrequencysynthesizerdependsoneachloopgain.Inthispaper,wepayattentiontothegainofaprogrammabledividerwhichisoneoftheimportantelementsofPLL,andproposeanewmethodforimprovingthegainofprogrammabledivider.Inordertoachievetheincreaseinthegainoftheprogrammabledivider,wealreadyproposedanewPLLfrequencysynthesizerwithmulti-programmabledividerbywhichthegainisincreasedevenwhenthesamereferencefrequencyandthesamedivisionratioasusualareused.InthispaperweproposeasimplePLLfrequencysynthesizerwithanauxiliaryprogrammabledividerwhichissuitableforLSIimplementation.Itwillbeshownbythetheoreticalconsiderationsandexperimentalresultsthatahigherspeedlock-uptimecanbeachieved.
1.Introduction
Asthecommunicationtechnologyadvances,aPLLfrequencysynthesizerisbeingrequiredwithhigherspeedlock-uptime,lowerpowerconsumptionandsmallersize.Variousmethodshavebeenproposedforattainingahigherspeedlock-uptimeinaPLLfrequencysynthesizer.
Inordertoachieveahigherspeedlock-uptime,itisnecessarytoincreasetheloopgainofthePLL.Forexample,thefractionaldivisionmethodhasbeenproposedtoincreasetheloopgain.However,sincethismethodusestwodifferentdivisionratiosalternately,morespuriousnoiseoccursaroundthereferencefrequencyduetothephasenoiseevenunderthesteadystateintheloop.InaconventionalPLL,oncethephasedetectororprogrammabledividerischosenasanelementofthePLL,theloopgainofPLLbecomesfixed.Inthispaper,weproposeasimplePLLfrequencysynthesizerwithanauxiliaryprogrammabledividermethodwhichcanattainahigherspeedlock-uptime,inordertomakeacircuitintoLSIimplementationeasily.ProposedPLLcanincreasetheloopgainwithouttheincreaseofreferencefrequency.EffectivenessofPLLwithmulti-programmabledividerandmulti-phasedetectorwillbeshownbythetheoreticalconsiderationsandexperimentalresults.
2.PLLfrequencysynthesizer
Figure1showstheblockdiagramoftheconventionalPhaseLockedLoop(PLL)frequencysynthesizer.Thiscircuithasbeenusedasalocaloscillatorofthetransmittersorreceiverandastimingelementsofdigitalequipment,andsoon.Itconsistsofaphasedetector,achargepump,aLowPassFilter(LPF),aVoltageControlledOscillator(VCO),andaprogrammabledivider.TheoutputfrequencyfvcoisanintegralmultipleofthereferencefrequencyfREFasgiveninEq.
(1).
3.TransientResponseofPLL
SincethePLLfrequencysynthesizeristhesecond-ordercontrolsystemincludingthefeedbackelement,wecananalyzeitbasedontheautomaticcontroltheory.InFig.1,thetransferfunctionsofaphasedetector,VCOandaprogrammabledivideraregivenbyKφ,Kvco,and1/N,respectively.Kφ,andKvcoshowsensitivityofphasedetectorandVCO,and1/Nisthedivisionratioofaprogrammabledivider.ThetotalgainM(s)ofPLLisgivenbyEq.
(2)usingabovetransferfunctions.
where,F(s)isthegainofLPF,andKistheloopgain.Inthispapergivenby
LetusconsiderthetransientresponseoftheactiveLPFinFig.2.ThetransferfunctionF(s)ofLPFisgivenby
where,
SubstitutionofEq.(4)intoEq.
(2)gives
where,
ωnisthenaturalangularfrequencyandζisthedampingfactor.Thetransientresponseofthesecond-ordersystemisdeterminedby
theseparameters.
Letusconsiderthetransientresponseforthefrequencystepinputfunctiongivenby△ω/s2.PerforminganInverseLaplaceTransform.wehave
Now,wemayneglectthecasesofζ=1andζ>1,andconsiderthecaseofζ<1.Theincreaseinωn,thatisincreaseinKordecreasein§,isconsideredtobeeffectiveforimprovingthelock-uptimedefinedinFig.3.Intheproposedmethod,thegainoftheprogrammabledivider1/Nisincreasedeighttimesbiggerthanthatoftheconventionalmethod.
4.Multi-programmabledividermethod
4.1Increaseofgaininprogrammable
ItisevidentthattheincreaseofωnbytheincreaseofthetotalloopgainKorthedividerdecreaseofτ1isnecessaryforimprovingoflock-uptime.ItcanbeseenfromEq.(3)thattheincreaseofKφ,Kvcoand1/NleadstotheincreaseofK.Inthispaper,weproposeanewmulti-programmabledividermethodasameanofenhancing1/N.
4.2Multi-programmabledividersmethod
Fig.4showstheblockdiagramofthePLLfrequencysynthesizerwithmulti-programmabledividersandFig.6istheoperationtimingchartofphasedetectors.Itiscomposedofeightprogrammabledividers,eightphasedetectorsandeightchargepumps.Thereferencesignalswhichareshiftedrespectivelybyusingthedelaycircuitarefedtoeachphasedetector.Itispossibletoachievehigh-speedlockuptimeattheexpenseofnumberofprogrammabledividers.Consequently,thepowerconsumptionandthescaleofthecircuitbecomesbigger.
'
Fig.4PLLfrequencysynthesizerwithmulti-programmabledivider.
4.3Auxiliaryprogrammabledivider
Fig.5showstheblockdiagramoftheproposedmethodusinganewlydevelopedauxiliaryprogrammabledividerandadecoder.Itisequivalenttoaprogrammabledividerwitheightoutput,andcanreplacetheeightprogrammabledividersinFig.4.Fig.6isalsothetimingchartinthiscase.WhenthedivisionratioisD,fVCOisdividedbyD/8throughNormalProgrammableDivider(NormalPD)whoseoutputfrequencyisfv'.Then,fv'isdividedbyeightanddistributedtoeightoutputsthroughtheauxiliaryProgrammabledivider(AuxiliaryPD)andmulti-outputdecoderasshowninFig.7.Then,eachreferencesignalandfeedbacksignalarecomparedeachotherindependently.Inaconventionalphasecomparator,thephasedetectorbecomesthestateofstandbyafterthecomparisonoperationuntiltherisingedgeofthefollowingreferencesignalcomes.However,intheproposedmethod,successivecomparisonoperationsareperformedinthestandbyofphasedetector1.Inaddition,incasethatthephasedifferenceislongerthanonecycleofthereferencesignal,PuorPdsignaloverlapsatthesametimebecausethechargepumpiscomposedofeight-foldasshowninFig.4and6.Therefore,theamountofthechargeanddischargetoLPFaremultipliedbyafactoroffourcomparedwiththecaseofPuorPdinasinglesystem.
VCOoutputfvcoisfedtoeachprogrammabledividerthroughtherespectivegate.Aprogrammabledivideriscomposedofeight-foldPD1-PD8,wherefvcoisdividedindependently.Then,thephasecomparisonis
Fig.5Auxiliaryprogrammabledividermethod
Fig.6TimingchartofPhasedetectors
Fig.7TimingchartofMulti-outputdecoder
4.4Effectofloopgainonlock-uptime
Next,weexplainthefour-foldexampleinthefollowinginordertomakeapracticaluse.
Fig.8Effectofloopgainonlock-uptime.
Sinceaprogrammabledividerhasbeencomposedfour-foldintheproposedmethod,theloopgainKbecomesfourtimesbiggerthanthatoftheconventionalmethod.Now,InEq.(3),UNbecomes(4*1/N).AnalyzingitinsimilarwayasfromEq.
(2)toEq.(9),wehave
Therefore,thelock-uptimeofPLLbecomesfourtimeshigherthantheconventionalmethodasshowninFig.8.
Themostimportantpointisthatthelockuptimebytheproposedmethodbecomesfourtimeshigherthanconventionalunderthesamereferencefrequency.Afractional-Ndivisionmethodisalsointroducedinordertospeedupthelockuptimewithhigherreferencefrequency.Theproposedmethodisalsoapplicabletoafractional-Nprogrammabledividertoattainafasterlockuptime.
5.Experimentalresults
Figs9and10aretheexperimentalresultsofthelock-uptimebytheconventionalmethodandtheproposedmethod,respectively.WeusedtheAMfrequencybandtomeasureabasicperformancecharacteristicoftheproposedPLL.Thereferencefrequencyl0kHzandfrequencyshiftfrom800kHzto2.2MHzaresetintheexperiment.Wecanseethatthefrequencylock-uptimeofaconventionalmethodandofaproposedmethodareabout8.0msand2.0ms,respectively.Fig.11showsfrequencyspuriouscharacteristicsoftheproposedPLLfrequencysynthesizerwhentheloopisinasteadystate.Itisobservedfromtheseexperimentalresultsthattheproposedmethodcanachieveahigherspeedlock-uptimekeepinggoodspuriouscharacteristics.
6.Conclusion
Inthispaper,wehaveproposedanewPLLfrequencysynthesizerwhichcanincreasetheloopgainbyusingfourprogrammabledividerskeepingsamereferencefrequencyanddivisionratioasconventional.Ithasbeenobservedfromtheexperimentalresultthatahigherspeedlock-uptimecanbeachievedbyusingtheproposedmethod.Inspiteofusingfourphasedetectorsandchargepumps,aprogrammabledividercanoperateatthesinglemode.Thereforethepowerconsumptionmustismuchsmallerthanbefore.
Fig.9Lock-uptime(Conventional).
Fig.10Lock-uptime(Proposedmethod)
Fig.11Spuriouscharacteristics.
Reference
[l]Y.Sumi,K.Syoubu,S.Obote,andY.Fukui,"PLLFrequencySynthesizerUsingMulti-PhaseDetector,"TechnicalReportofIEEJ,ECT-97-14,pp.77-82,Jan.1997.
[2]M.Hagiwara,andY.Suzuki,"PracticalPLLfrequencysynthesizer,''Sougou-denshiinc.,1995.
[3]Y.Sumi,S.Obote,K.Narai,K.Tsuda,K.Syoubu,andY.Fukui,"FastFrequencyAcquisitioninthePLLFrequencySynthe-sizerSuppressingtheTransientResponseoftheSecondOrderSystem,"TechnicalReportofIEICE,CAS96-98,pp.69-76,Mar.1997.
[4]Y.Sumi,S.Obote,K.Tsuda,K.Syoubu,andY.Fukui,"ANewLowPassFilterforthe
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