电子时钟设计EDA.docx
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电子时钟设计EDA.docx
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电子时钟设计EDA
基于EDA实验
设计报告
课程名称EDA技术及应用
任课教师安亚军
设计题目数字钟
班级电子Z-082班
姓名胡学亮
学号084122
日期2010年6月11日
目录
1题目要求1
1.1设计要求(数字钟的功能)1
1.2目的1
1.3硬件要求2
1.4实验原理2
1.5实验内容及步骤2
2设计内容3
2.1底层文件设计3
2.2顶层原理图设计3
3心得体会3
EDA数字钟课程设计
1.题目要求
1.1设计要求(数字钟的功能)
具有时、分显示功能(用数码管显示),以24小时循环计时。
具有清零、调节小时、分钟的功能。
具有整点(正小时)报时同时用多颗LED花样显示秒的功能。
运用多层次化设计方式,底层元件用VHDL编写,顶层元件用原理图法连线。
写出课程设计报告,包括设计源程序代码,顶层原理图及必要的文字说明。
1.2目的
掌握多为计数器相连的方法。
掌握十进制、六进制、二十四进制计数器的设计方法。
掌握扬声器的驱动及报时的设计。
LED的花样显示。
掌握CPLD技术的层次化设计方法。
1.3硬件要求
主芯片AlteraEPF10K10LC84-4。
8个LED灯。
扬声器。
4位数码显示器。
8个按键开关。
1.4实验原理
在同一CPLD芯片上集成了如下电路模块
时钟技术:
秒······60进制BCD码技计数;
分······60进制BCD码技计数;
时······24进制BCD码技计数;
同时整个计数器有清零、调时、调分功能。
在接近整数时能提供报时信息。
扬声器在整点时有报时驱动信号产生(响声持续多长时间)。
LED灯按个人口味在整点时有花样显示信号产生。
1.5实验内容及步骤
根据电路特点运用层次设计概念设计,将此设计任务分成若干模块,规定每一模块的功能和各模块之间接口。
加深层次化设计概念。
了解软件的元件管理深层含义,以及模块元件之间的连接概念,对于不同目录下的统一设计,如何熔合。
2.设计内容
2.1底层文件设计
60进制秒和60进制分的vhdl程序和仿真图如下
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcoutm60IS
PORT(ci:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
load:
INSTD_LOGIC;
enb:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
clk:
INSTD_LOGIC;
co:
OUTSTD_LOGIC;
mn:
OUTSTD_LOGIC;
qh:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);
ql:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));
ENDcoutm60;
ARCHITECTUREbehaveOFcoutm60IS
SIGNALm:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALn:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
co<='1'WHEN(qh="0101"ANDql="1001"ANDci='1')ELSE
'0';
mn<='1'WHEN(qh=m(3DOWNTO0)ANDql=n(3DOWNTO0)ANDn/="0000"ANDreset='0'ANDload='0')ELSE
'0';
PROCESS(clk,reset)
BEGIN
IF(reset='1')THEN
qh<="0000";
ql<="0000";
ELSIF(clk'EVENTANDclk='1')THEN
IF(load='1'ANDenb='0')THEN
qh<=d(7DOWNTO4);
ql<=d(3DOWNTO0);
ELSE
IF(load='1'ANDenb='1')THEN
m<=d(7DOWNTO4);
n<=d(3DOWNTO0);
ENDIF;
IF(ci='1')THEN
IF(ql=9)THEN
ql<="0000";
IF(qh=5)THEN
qh<="0000";
ELSE
qh<=qh+1;
ENDIF;
ELSE
ql<=ql+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDbehave;
分析该仿真图;
Reset(清零)、load(预置)、enb(定时使能)、clk(时钟)、ci(工作使能)、d(设置预置数或定时数)、mn(到定的数时输出)、co(进位)、ql(60进制低位)、qh(60进制高位),enb和load同时为‘1’时定时。
24进制vhdl程序和仿真图如下
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYcout24IS
PORT(ci:
INSTD_LOGIC;
reset:
INSTD_LOGIC;
load:
INSTD_LOGIC;
enb:
INSTD_LOGIC;
d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
clk:
INSTD_LOGIC;
co:
OUTSTD_LOGIC;
mn:
OUTSTD_LOGIC;
qh:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0);
ql:
BUFFERSTD_LOGIC_VECTOR(3DOWNTO0));
ENDcout24;
ARCHITECTUREbehaveOFcout24IS
SIGNALm:
STD_LOGIC_VECTOR(3DOWNTO0);
SIGNALn:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
co<='1'WHEN(qh="0010"ANDql="0011"ANDci='1')ELSE
'0';
mn<='1'WHEN(qh=m(3DOWNTO0)ANDql=n(3DOWNTO0)ANDreset='0'ANDload='0')ELSE
'0';
PROCESS(clk,reset)
BEGIN
IF(reset='1')THEN
qh<="0000";
ql<="0000";
ELSIF(clk'EVENTANDclk='1')THEN
IF(load='1')THEN
IF(enb='0')THEN
qh<=d(7DOWNTO4);
ql<=d(3DOWNTO0);
ELSE
m<=d(7DOWNTO4);
n<=d(3DOWNTO0);
ENDIF;
ELSIF(ci='1')THEN
IF(qh=0ORqh=1)THEN
IF(ql=9)THEN
ql<="0000";
qh<=qh+1;
ELSE
ql<=ql+1;
ENDIF;
ELSIF(qh=2)THEN
IF(ql=3)THEN
ql<="0000";
qh<="0000";
ELSE
ql<=ql+1;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
ENDPROCESS;
ENDbehave;
分析该仿真图;
Reset(清零)、load(预置)、enb(定时使能)、clk(时钟)、ci(工作使能)、d(设置预置数或定时数)、mn(到定的数时输出)、co(进位)、ql(60进制低位)、qh(60进制高位),enb和load同时为‘1’时定时。
music的程序和仿真图如下
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitymusicis
port(inclk:
instd_logic;
spk:
bufferstd_logic);
endmusic;
architecturebehaveofmusicis
signaltone:
std_logic_vector(10downto0);
signaltone_count:
std_logic_vector(10downto0);
signaltone_index:
integerrange0to15;
signalclk10_count:
std_logic_vector(17downto0);
signaltime:
integerrange0to150;
signalclk:
std_logic;
signalclk10:
std_logic;
begin
PROCESS(inclk)--generate2Mhzclocksignal
variablecnt1:
INTEGERRANGE0TO29;
BEGIN
IFinclk='1'ANDinclk'eventTHEN
IFcnt1=29THENcnt1:
=0;
ELSE
IFcnt1<20THENclk<='1';
ELSEclk<='0';
ENDIF;
cnt1:
=cnt1+1;
ENDIF;
ENDIF;
ENDPROCESS;
process(clk)--generate10hzclocksignal
begin
if(clk'eventandclk='1')then
clk10_count<=clk10_count+1;
if(clk10_count=16#3fff#)then
clk10<=notclk10;
endif;
endif;
endprocess;
process(clk10)
begin
if(clk10'eventandclk10='1')then
if(time=150)then
time<=0;
else
time<=time+1;
endif;
endif;
endprocess;
process(clk10)
begin
if(clk10'eventandclk10='1')then
casetimeis
when0=>tone_index<=3;
when1=>tone_index<=3;
when2=>tone_index<=3;
when3=>tone_index<=3;
when4=>tone_index<=5;
when5=>tone_index<=5;
when6=>tone_index<=5;
when7=>tone_index<=6;
when8=>tone_index<=8;
when9=>tone_index<=8;
when10=>tone_index<=8;
when11=>tone_index<=9;
when12=>tone_index<=6;
when13=>tone_index<=8;
when14=>tone_index<=5;
when15=>tone_index<=5;
when16=>tone_index<=12;
when17=>tone_index<=12;
when18=>tone_index<=12;
when19=>tone_index<=15;
when20=>tone_index<=13;
when21=>tone_index<=12;
when22=>tone_index<=10;
when23=>tone_index<=12;
when24=>tone_index<=9;
when25=>tone_index<=9;
when26=>tone_index<=9;
when27=>tone_index<=9;
when28=>tone_index<=9;
when29=>tone_index<=9;
when30=>tone_index<=0;
when31=>tone_index<=0;
when32=>tone_index<=9;
when33=>tone_index<=9;
when34=>tone_index<=9;
when35=>tone_index<=10;
when36=>tone_index<=7;
when37=>tone_index<=7;
when38=>tone_index<=6;
when39=>tone_index<=6;
when40=>tone_index<=5;
when41=>tone_index<=5;
when42=>tone_index<=5;
when43=>tone_index<=6;
when44=>tone_index<=8;
when45=>tone_index<=8;
when46=>tone_index<=9;
when47=>tone_index<=9;
when48=>tone_index<=3;
when49=>tone_index<=3;
when50=>tone_index<=8;
when51=>tone_index<=8;
when52=>tone_index<=6;
when53=>tone_index<=5;
when54=>tone_index<=6;
when55=>tone_index<=8;
when56=>tone_index<=5;
when57=>tone_index<=5;
when58=>tone_index<=5;
when59=>tone_index<=5;
when60=>tone_index<=5;
when61=>tone_index<=5;
when62=>tone_index<=0;
when63=>tone_index<=0;
when64=>tone_index<=10;
when65=>tone_index<=10;
when66=>tone_index<=10;
when67=>tone_index<=12;
when68=>tone_index<=7;
when69=>tone_index<=7;
when70=>tone_index<=9;
when71=>tone_index<=9;
when72=>tone_index<=6;
when73=>tone_index<=8;
when74=>tone_index<=5;
when75=>tone_index<=5;
when76=>tone_index<=5;
when77=>tone_index<=5;
when78=>tone_index<=5;
when79=>tone_index<=5;
when80=>tone_index<=5;
when81=>tone_index<=0;
when82=>tone_index<=0;
when83=>tone_index<=3;
when84=>tone_index<=5;
when85=>tone_index<=3;
when86=>tone_index<=5;
when87=>tone_index<=5;
when88=>tone_index<=6;
when89=>tone_index<=7;
when90=>tone_index<=9;
when91=>tone_index<=6;
when92=>tone_index<=6;
when93=>tone_index<=6;
when94=>tone_index<=6;
when95=>tone_index<=6;
when96=>tone_index<=6;
when97=>tone_index<=5;
when98=>tone_index<=6;
when99=>tone_index<=8;
when100=>tone_index<=8;
when101=>tone_index<=8;
when102=>tone_index<=9;
when103=>tone_index<=12;
when104=>tone_index<=12;
when105=>tone_index<=12;
when106=>tone_index<=10;
when107=>tone_index<=9;
when108=>tone_index<=9;
when109=>tone_index<=10;
when110=>tone_index<=9;
when111=>tone_index<=8;
when112=>tone_index<=8;
when113=>tone_index<=6;
when114=>tone_index<=5;
when115=>tone_index<=3;
when116=>tone_index<=3;
when117=>tone_index<=3;
when118=>tone_index<=3;
when119=>tone_index<=8;
when120=>tone_index<=8;
when121=>tone_index<=8;
when122=>tone_index<=8;
when123=>tone_index<=6;
when124=>tone_index<=8;
when125=>tone_index<=6;
when126=>tone_index<=5;
when127=>tone_index<=3;
when128=>tone_index<=5;
when129=>tone_index<=6;
when130=>tone_index<=8;
when131=>tone_index<=5;
when132=>tone_index<=5;
when133=>tone_index<=5;
when134=>tone_index<=5;
when135=>tone_index<=5;
when136=>tone_index<=5;
when137=>tone_index<=5;
when138=>tone_index<=0;
when139=>tone_index<=0;
whenothers=>tone_index<=0;
endcase;
endif;
endprocess;
process(tone_index)
begin
casetone_indexis
when0=>tone<="11111111111";
when1=>tone<="01100000101";
when2=>tone<="01110010000";
when3=>tone<="10000001100";
when5=>tone<="10010101101";
when6=>tone<="10100001010";
when7=>tone<="10101011100";
when8=>tone<="10110000010";
when9=>tone<="10111001000";
when10=>tone<="11000000110";
when12=>tone<="11001010110";
when13=>tone<="11010000100";
when15=>tone<="11011000000";
whenothers=>tone<="11111111111";
endcase;
endprocess;
process(clk)--controlthefrequenceofthespeaker
begin
if(clk'eventandclk='1')then
if(tone_count=16#7ff#)then
tone_count<=tone;
if(tone<2047)then
spk<=notspk;
endif;
else
tone_count<=tone_count+1;
endif;
endif;
endprocess;
endbehave;
分析该仿真图
Inclk(50Mhz脉冲)、spk(输出梁祝音乐)。
Baoshi的程序和仿真图如下
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybaoshiis
port(m1,m0,s1,s0:
instd_logic_vector(3downto0);
sig500,sig1k:
outstd_logic);
endbaoshi;
architecturebehaveofbaoshiis
begin
process(m0)
begin
sig500<='0';
sig1k<='0';
ifm1="0101"andm0="1001"then
ifs1="0101"and(s0="0000"ors0="0010"ors0="0100"ors0="0110"ors0="1000")then
sig500<='1';
else
sig500<='0';
endif;
endif;
ifm1="0000"andm0="0000"ands1="0000"a
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