TMS320x2833x Multichannel Buffered Serial Port McBSP第八章外文.docx
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TMS320x2833x Multichannel Buffered Serial Port McBSP第八章外文.docx
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TMS320x2833xMultichannelBufferedSerialPortMcBSP第八章外文
Chapter8TransmitterConfiguration
ToconfiguretheMcBSPtransmitter,performthefollowingprocedure:
1.PlacetheMcBSP/transmitterinreset(seeSection8.2).
2.ProgramtheMcBSPregistersforthedesiredtransmitteroperation(seeSection8.1).
3.Takethetransmitteroutofreset(seeSection8.2).
8.1ProgrammingtheMcBSPRegistersfortheDesiredTransmitterOperation
ThefollowingisalistofimportanttaskstobeperformedwhenyouareconfiguringtheMcBSPtransmitter.EachtaskcorrespondstooneormoreMcBSPregisterbitfields.
•Globalbehavior:
SetthetransmitterpinstooperateasMcBSPpins.
Enable/disablethedigitalloopbackmode.
Enable/disabletheclockstopmode.
Enable/disabletransmitmultichannelselection.
•Databehavior:
Choose1or2phasesforthetransmitframe.
Setthetransmitwordlength(s).
Setthetransmitframelength.
Enable/disablethetransmitframe-synchronizationignorefunction.
Setthetransmitcompandingmode.
Setthetransmitdatadelay.
SetthetransmitDXENAmode.
Setthetransmitinterruptmode.
•Frame-synchronizationbehavior:
Setthetransmitframe-synchronizationmode.
Setthetransmitframe-synchronizationpolarity.
SettheSRGframe-synchronizationperiodandpulsewidth.
•Clockbehavior:
Setthetransmitclockmode.
Setthetransmitclockpolarity.
SettheSRGclockdivide-downvalue.
SettheSRGclocksynchronizationmode.
SettheSRGclockmode(chooseaninputclock).
SettheSRGinputclockpolarity.
8.2ResettingandEnablingtheTransmitter
Thefirststepofthetransmitterconfigurationprocedureistoresetthetransmitter,andthelaststepistoenablethetransmitter(totakeitoutofreset).Table8-1describesthebitsusedforbothofthesesteps.
Table8-1.RegisterBitsUsedtoPlaceTransmitterinResetFieldDescriptions(continued)
Register
Bit
Field
Value
Description
SPCR2
0
XRST
01
TransmitterresetTheserialporttransmitterisdisabledandintheresetstate.Theserialporttransmitterisenabled.
Table8-1Table8-1.RegisterBitsUsedtoPlaceTransmitterinResetFieldDescriptions
8.2.1ResetConsiderations
Theserialportcanberesetinthefollowingtwoways:
1.ADSPreset(XRSsignaldrivenlow)placesthereceiver,transmitter,andsamplerategeneratorinreset.Whenthedeviceresetisremoved,GRST=FRST=RRST=XRST=0,keepingtheentireserialportintheresetstate.
2.TheserialporttransmitterandreceivercanberesetdirectlyusingtheRRSTandXRSTbitsintheserialportcontrolregisters.ThesamplerategeneratorcanberesetdirectlyusingtheGRSTbitinSPCR2.
3.WhenusingtheDMA,theorderinwhichMcBSPeventsmustoccurisimportant.DMAchannelandperipheralinterruptsmustbeconfiguredpriortoreleasingtheMcBSPtransmitterfromreset.ThereasonforthisisthatanXRDYisfiredwhenXRST=1.TheXRDYsignalstheDMAtostartcopyingdatafromthebufferintothetransmitregister.IftheMcBSPtransmitterisreleasedfromresetbeforetheDMAchannelandperipheralinterruptsareconfigured,theXRDYsignalsbeforetheDMAchannelcanreceivethesignal;therefore,theDMAdoesnotmovethedatafromthebuffertothetransmitregister.TheDMAPERINTFLGisedge-sensitiveandwillfailtorecognizetheXRDY,whichiscontinuouslyhigh.
FormoredetailsaboutMcBSPresetconditionsandeffects,seeSection9.2,ResettingandInitializingaMcBSP.
8.3SettheTransmitterPinstoOperateasMcBSPPins
ToconfigureapinforitsMcBSPfunction,youshouldconfigurethebitsoftheGPxMUXnregisterappropriately.Inadditiontothis,bits12and13ofthePCRregistermustbesetto0.Thesebitsaredefinedasreserved.
8.4Enable/DisabletheDigitalLoopbackMode
TheDLBbitdetermineswhetherthedigitalloopbackmodeison.DLBisdescribedinTable8-2.
8.4.1DigitalLoopbackMode
Inthedigitalloopbackmode,thereceivesignalsareconnectedinternallythroughmultiplexerstothecorrespondingtransmitsignals,asshowninTable8-3.ThismodeallowstestingofserialportcodewithasingleDSPdevice;theMcBSPreceivesthedataittransmits.
Table8-3.ReceiveSignalsConnectedtoTransmitSignalsinDigitalLoopbackMode
8.5Enable/DisabletheClockStopMode
TheCLKSTPbitsdeterminewhethertheclockstopmodeison.CLKSTPisdescribedinTable8-4.
Table8-4.RegisterBitsUsedtoEnable/DisabletheClockStopMode
8.5.1ClockStopMode
TheclockstopmodesupportstheSPImaster-slaveprotocol.IfyoudonotplantousetheSPIprotocol,youcanclearCLKSTPtodisabletheclockstopmode.
Intheclockstopmode,theclockstopsattheendofeachdatatransfer.Atthebeginningofeachdatatransfer,theclockstartsimmediately(CLKSTP=10b)orafterahalf-cycledelay(CLKSTP=11b).TheCLKXPbitdetermineswhetherthestartingedgeoftheclockontheMCLKXpinisrisingorfalling.TheCLKRPbitdetermineswhetherreceivedataissampledontherisingorfallingedgeoftheclockshownontheMCLKRpin.
Table8-5summarizestheimpactofCLKSTP,CLKXP,andCLKRPonserialportoperation.Intheclockstopmode,thereceiveclockistiedinternallytothetransmitclock,andthereceiveframe-synchronizationsignalistiedinternallytothetransmitframe-synchronizationsignal.
Table8-5.EffectsofCLKSTP,CLKXP,andCLKRPontheClockScheme
BitSettingsClockScheme
8.6Enable/DisableTransmitMultichannelSelection
Formoredetails.seeSection5.7TransmintMultichannelSelectionModes
8.7ChooseOneorTwoPhasesforTransmitFrame
8.8.1WordLengthBits
Eachframecanhaveoneortwophases,dependingonthevaluethatyouloadintotheRPHASEbit.Ifasingle-phaseframeisselected,XWDLEN1selectsthelengthforeveryserialwordtransmittedintheframe.Ifadual-phaseframeisselected,XWDLEN1determinesthelengthoftheserialwordsinphase1oftheframe,andXWDLEN2determinesthewordlengthinphase2oftheframe.
8.9.1SelectedFrameLength
Thetransmitframelengthisthenumberofserialwordsinthetransmitframe.Eachframecanhaveoneortwophases,dependingonthevaluethatyouloadintotheXPHASEbit.
Ifasingle-phaseframeisselected(XPHASE=0),theframelengthisequaltothelengthofphase1.Ifadual-phaseframeisselected(XPHASE=1),theframelengthisthelengthofphase1plusthelengthofphase2.
The7-bitXFRLENfieldsallowupto128wordsperphase.SeeTable8-10forasummaryofhowtocalculatetheframelength.Thislengthcorrespondstothenumberofwordsorlogicaltimeslotsorchannelsperframe-synchronizationpulse.
Note:
ProgramtheXFRLENfieldswith[wminus1],wherewrepresentsthenumberofwordsperphase.Forexample,ifyouwantaphaselengthof128wordsinphase1,load127intoXFRLEN1.
Table8-10.HowtoCalculateFrameLength
8.10Enable/DisabletheTransmitFrame-SynchronizationIgnoreFunction
Table8-11.RegisterBitUsedtoEnable/DisabletheTransmitFrame-SynchronizationIgnoreFunction
8.10.1UnexpectedFrame-SynchronizationPulsesandFrame-SynchronizationIgnore
Ifaframe-synchronizationpulsestartsthetransferofanewframebeforethecurrentframeisfullytransmitted,thispulseistreatedasanunexpectedframe-synchronizationpulse.WhenXFIG=1,normaltransmissioncontinueswithunexpectedframe-synchronizationsignalsignored.WhenXFIG=0andanunexpectedframe-synchronizationpulseoccurs,theserialport:
1.Abortsthepresenttransmission
2.SetsXSYNCERRto1inSPCR2
3.Reinitiatestransmissionofthecurrentwordthatwasaborted
Formoredetailsabouttheframe-synchronizationerrorcondition,seeSection4.6,UnexpectedTransmitFrame-SynchronizationPulse.
8.10.2ExamplesShowingtheEffectsofXFIG
Figure8-1showsanexampleinwhichwordBisinterruptedbyanunexpectedframe-synchronizationpulsewhen(R/X)FIG=0.Inthecaseoftransmission,thetransmissionofBisaborted(Bislost).Thisconditionisatransmitsynchronizationerror,whichsetstheXSYNCERRbit.NonewdatahasbeenwrittentoDXR[1,2];therefore,theMcBSPtransmitsBagain.
Figure8-1.UnexpectedFrame-SynchronizationPulseWith(R/X)FIG=0
IncontrastwithFigure8-1,Figure8-2showsMcBSPoperationwhenunexpectedframe-synchronizationsignalsareignored(when(R/X)FIG=1).Here,thetransferofwordBisnotaffectedbyanunexpectedframe-synchronizationpulse.
Figure8-2.UnexpectedFrame-SynchronizationPulseWith(R/X)FIG=1
8.11SettheTransmitCompandingModeTable8-12.RegisterBitsUsedtoSettheTransmitCompandingMode
8.11.1Companding
Companding(COMpressingandexPANDing)hardwareallowscompressionandexpansionofdataineitherµ-laworA-lawformat.ThecompandingstandardemployedintheUnitedStatesandJapanisµ-law.TheEuropeancompandingstandardisreferredtoasA-law.Thespecificationsforµ-lawandA-lawlogPCMarepartoftheCCITTG.711recommendation.
A-lawandµ-lawallow13bitsand14bitsofdynamicrange,respectively.Anyvaluesoutsidethisrangearesettothemostpositiveormostnegativevalue.Thus,forcompandingtoworkbest,thedatatransferredtoandfromtheMcBSPviatheCPUorDMAcontrollermustbeatleast16bitswide.
Theµ-lawandA-lawformatsbothencodedatainto8-bitcodewords.Compandeddataisalways8bitswide;theappropriatewordlengthbits(RWDLEN1,RWDLEN2,XWDLEN1,XWDLEN2)mustthereforebesetto0,indicatingan8-bitwideserialdatastream.Ifcompandingisenabledandeitheroftheframephasesdoesnothavean8-bitwordlength,compandingcontinuesasifthewordleng
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