SPIDiv.docx
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- 上传时间:2023-07-03
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- 页数:15
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SPIDiv.docx
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SPIDiv
//-------------------------------------------------------------------------------------------------------------------------
//Copyright(c)SamsungElectronicsCo.,Ltd.Allrightsreserved.
//-------------------------------------------------------------------------------------------------------------------------
//
//THISCODEANDINFORMATIONISPROVIDED"ASIS"WITHOUTWARRANTYOFANYKIND,EITHEREXPRESSEDORIMPLIED,
//INCLUDINGBUTNOTLIMITEDTOTHEIMPLIEDWARRANTIESOFMERCHANTABILITYAND/ORFITNESSFORAPARTICULARPURPOSE.
//
//ModuleName:
spi_priv.H
//
//Abstract:
SPIInterfaceRoutinesforSamsungS5PV210CPU
//
//Environment:
SamsungS5PV210/WinCE6.0
//
//2010/02/10asdfAddedFullduplexmode(Ver1.01)
//DefineSPI_FULL_DUPLEXinsourcesfiletousefullduplex
//2009/07/10asdfModifiedforsupporting3-CHofSPI
//
//-------------------------------------------------------------------------------------------------------------------------
#ifndef_SPI_PRIV_H_
#define_SPI_PRIV_H_
/*****************************************************************************
*Includefiles
*****************************************************************************/
#include
/*****************************************************************************
*Definitions
*****************************************************************************/
#defineSPI_MASTER_MODE1
#defineSPI_SLAVE_MODE0
#defineFIFO_EMPTY0x0
#defineRX_TRIG_LEVEL0
#defineWRITE_TIME_OUT_CONSTANT5000
#defineWRITE_TIME_OUT_MULTIPLIER1
#defineREAD_TIME_OUT_CONSTANT5000
#defineREAD_TIME_OUT_MULTIPLIER1
#defineSPI_WAIT_TIMEOUT(0x10000000)
#defineSPI_IS_TIMEOUT(count)((count&SPI_WAIT_TIMEOUT)?
TRUE:
FALSE)
#defineMASTER_CS_ENABLEpSPIregs->CS_SEL=0
#defineMASTER_CS_DISABLEpSPIregs->CS_SEL=1
#defineTRAIL_CNT(n)(((n)&0x3FF)<<19)
#defineSPI_POWER_ON(1<<21)
#defineSPI_SCLK_ON(1<<8)
#defineSPI_USBHOST_ON(1<<22)
#definePCLOCK(0)
#defineMPLL_CLOCK
(1)
#defineEPLL_CLOCK
(2)
#defineBASE_REG_SPI_OFFSET0x100000
#defineSPI_DMA_BUF_SIZE4096
//IOCTLCommands
#defineSPI_IOCTL_STARTCTL_CODE(FILE_DEVICE_SERIAL_PORT,0,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_STOPCTL_CODE(FILE_DEVICE_SERIAL_PORT,1,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_SET_CONFIGCTL_CODE(FILE_DEVICE_SERIAL_PORT,2,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_GET_CONFIGCTL_CODE(FILE_DEVICE_SERIAL_PORT,3,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_SET_CALLBACKCTL_CODE(FILE_DEVICE_SERIAL_PORT,10,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_CLR_CALLBACKCTL_CODE(FILE_DEVICE_SERIAL_PORT,11,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_IS_SLAVE_READYCTL_CODE(FILE_DEVICE_SERIAL_PORT,12,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_SERIAL_GET_WAIT_MASKCTL_CODE(FILE_DEVICE_SERIAL_PORT,20,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_SERIAL_SET_WAIT_MASKCTL_CODE(FILE_DEVICE_SERIAL_PORT,21,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_SERIAL_WAIT_ON_MASKCTL_CODE(FILE_DEVICE_SERIAL_PORT,22,METHOD_BUFFERED,FILE_ANY_ACCESS)
#defineSPI_IOCTL_FULL_DUPLEXCTL_CODE(FILE_DEVICE_SERIAL_PORT,23,METHOD_BUFFERED,FILE_ANY_ACCESS)
/////////////////////////////////////////////////////////////////////////////////////////
//RequiredRegistrySetting.
#definePC_REG_SPI_DEVICE_INDEXTEXT("DeviceArrayIndex")
/////////////////////////////////////////////////////////////////////////////////////////
typedefenum
{
SPI0=0,
SPI1=1,
SPI2=2,
INVALID
}SPI_CH_NUM;
/*****************************************************************************
*SPISFR
*****************************************************************************/
//SPI_REG+0x00CH_CFG
#defineHIGH_SPEED_MASK(1<<6)
#defineHIGH_SPEED_DIS(0<<6)
#defineHIGH_SPEED_EN(1<<6)
#defineSW_RST(1<<5)
#defineSPI_MASTER(0<<4)
#defineSPI_SLAVE(1<<4)
#defineCPOL_RISING(0<<3)
#defineCPOL_FALLING(1<<3)
#defineCPHA_FORMAT_A(0<<2)
#defineCPHA_FORMAT_B(1<<2)
#defineRX_CH_OFF(0<<1)
#defineRX_CH_ON(1<<1)
#defineTX_CH_OFF(0<<0)
#defineTX_CH_ON(1<<0)
//SPI_REG+0x04CLK_CFG
#defineCLKSEL_PCLK(0<<9)
#defineCLKSEL_SPI_EXT_CLK(1<<9)
#defineENCLK_DISABLE(0<<8)
#defineENCLK_ENABLE(1<<8)
//SPI_REG+0x08MODE_CFG
#defineCH_SIZE_BYTE(0<<29)
#defineCH_SIZE_HALF(1<<29)
#defineCH_SIZE_WORD(2<<29)
#defineBUS_SIZE_BYTE(0<<17)
#defineBUS_SIZE_HALF(1<<17)
#defineBUS_SIZE_WORD(2<<17)
#defineDMA_SINGLE(0<<0)
#defineDMA_4BURST(1<<0)
#defineRX_DMA_ON(1<<2)
#defineTX_DMA_ON(1<<1)
#defineMODE_DEFAULT(0)
//SPI_REG+0x0CCS_REG
//SPI_REG+0x10SPI_INT_EN
#defineINT_TRAILING(1<<6)
#defineINT_RX_OVERRUN(1<<5)
#defineINT_RX_UNDERRUN(1<<4)
#defineINT_TX_OVERRUN(1<<3)
#defineINT_TX_UNDERRUN(1<<2)
#defineINT_RX_FIFORDY(1<<1)
#defineINT_TX_FIFORDY(1<<0)
//SPI_REG+0x14SPI_STATUS
#defineTX_DONE(1<<25)
#defineTRAILCNT_ZERO(1<<24)
#defineRX_OVERRUN(1<<5)
#defineRX_UNDERRUN(1<<4)
#defineTX_OVERRUN(1<<3)
#defineTX_UNDERRUN(1<<2)
#defineRX_FIFORDY(1<<1)
#defineTX_FIFORDY(1<<0)
//SPI_REG+0x18SPI_TX_DATA
//SPI_REG+0x1CSPI_RX_DATA
//SPI_REG+0x20PACKET_CNT
#definePACKET_CNT_EN(1<<16)
//SPI_REG+0x24PENDING_CLR_REG
#defineTX_UNDERRUN_CLR(1<<4)
#defineTX_OVERRUN_CLR(1<<3)
#defineRX_UNDERRUN_CLR(1<<2)
#defineRX_OVERRUN_CLR(1<<1)
#defineTRAILING_CLR(1<<0)
//SPI_REG+0x28SWAP_CFG_REG
#defineRX_HALF_SWAP(1<<7)
#defineRX_BYTE_SWAP(1<<6)
#defineRX_BIT_SWAP(1<<5)
#defineRX_SWAP_EN(1<<4)
#defineTX_HALF_SWAP(1<<3)
#defineTX_BYTE_SWAP(1<<2)
#defineTX_BIT_SWAP(1<<1)
#defineTX_SWAP_EN(1<<0)
//SPI_REG+0x2CFB_CLK_SEL_REG
//NOTE:
90degreephaselaggingmeans5nsdelayin50MHzoperatingfrequency
#defineDO_NOT_USE_FEEDBACK_CLOCK(0x0)
#defineFB_CLK_WITH_90_DEGREE_PHASE_LAG(0x1)
#defineFB_CLK_WITH_180_DEGREE_PHASE_LAG(0x2)
#defineFB_CLK_WITH_270_DEGREE_PHASE_LAG(0x3)
//#definePADDRFIX(1<<24)
typedefenum{
SPI_FORMAT_0,
SPI_FORMAT_1,
SPI_FORMAT_2,
SPI_FORMAT_3
}SPI_FORMAT;
typedefenum{
SPI_BYTE_BUS=0,
SPI_HWORD_BUS,
SPI_WORD_BUS,
SPI_DWORD_BUS
}SPI_BUS_WIDTH;
typedefenum{
SPI_BYTE_CHN,
SPI_HWORD_CHN,
SPI_WORD_CHN,
SPI_DWORD_CHN
}SPI_CHN_WIDTH;
typedefenum{
SPI_SWAP_DISABLE,
SPI_BIT_SWAP=2,
SPI_BYTE_SWAP=4,
SPI_WORD_SWAP=8
}SPI_SWAP_SIZE;
/*
typedefstruct{
PVOIDVirtualAddress;
UINT32PhysicalAddress;
}SPI_DMA_BUFFER,*PSPI_DMA_BUFFER;*/
typedefenum{
STATE_TIMEOUT,
STATE_READING,
STATE_RXDMA,
STATE_RXINTR,
STATE_WRITING,
STATE_TXDMA,
STATE_TXINTR,
STATE_CONTROLLING,
STATE_RXBUFFERRING,
STATE_TXBUFFERRING,
STATE_IDLE,
STATE_CANCELLING,
STATE_INIT,
STATE_FULLDUPLEX,
STATE_ERROR
}SPI_STATUS;
typedefenum{
SPI_NO_ERROR=0,
RECOVERABLE_ERROR=100,
STATE_CHECKING_ERROR,
PARAM_CHECKING_ERROR,
TX_TIMEOUT_ERROR,
RX_TIMEOUT_ERROR,
UNRECOVERABLE_ERROR=200,
UNDEFINED_ERROR=999
}SPI_ERROR;
typedefstruct{
PBYTEpStrMem;
PBYTEpEndMem;
PBYTEpCurMem;
DWORDdwMemSize;
DWORDdwDataSize;
DWORDdwUsedSize;
DWORDdwUnusedSize;
BOOLbNeedBuffering;
}SPI_BUFFER;
#ifdefSPI_EX_GPIO_CALLBACK
typedefBOOL(*SPI_CALLBACK)(PSPI_PRIVATE_CONTEXT);
#endif
typedefstruct{
DWORDdwMode;
BOOLbUseRxFIFO;
BOOLbUseRxDMA;
BOOLbUseRxIntr;
DWORDdwRxTrigger;
SPI_BUS_WIDTHRxBusWidth;
SPI_CHN_WIDTHRxChnWidth;
SPI_SWAP_SIZERxSwap;
BOOLbRxDMABurst;
BOOLbUseTxFIFO;
BOOLbUseTxDMA;
BOOLbUseTxIntr;
DWORDdwTxTrigger;
SPI_BUS_WIDTHTxBusWidth;
SPI_CHN_WIDTHTxChnWidth;
SPI_SWAP_SIZETxSwap;
BOOLbTxDMABurst;
DWORDdwLLICount;//forDMALLIsetting
BOOLbLoopedLLI;
DWORDdwLineStrength;
DWORDdwFBClkSel;
DWORDdwPrescaler;
DWORDdwTimeOutVal;
SPI_FORMATFormat;
}SPI_SET_CONFIG,*PSPI_SET_CONFIG;
typedefstruct{
DWORDdwMode;
BOOLbUseRxFIFO;
BOOLbUseRxDMA;
BOOLbUseRxIntr;
DWORDdwRxTrigger;
SPI_BUS_WIDTHRxBusWidth;
SPI_CHN_WIDTHRxChnWidth;
SPI_SWAP_SIZERxSwap;
BOOLbRxDMABurst;
BOOLbUseTxFIFO;
BOOLbUseTxDMA;
BOOLbUseTxIntr;
DWORDdwTxTrigger;
SPI_BUS_WIDTHTxBusWidth;
SPI_CHN_WIDTHTxChnWidth;
SPI_SWAP_SIZETxSwap;
BOOLbTxDMABurst;
DWORDdwLLICount;//forDMALLIsetting
BOOLbLoopedLLI;
DWORDdwPrescaler;
DWORDdwTimeOutVal;
SPI_FORMATFormat;
}SPI_GET_CONFIG,*PSPI_GET_CONFIG;
typedefstruct{
DMA_CH_CONTEXTg_OutputDMA;
DMA_CH_CONTEXTg_InputDMA;
UINTDmaDstAddress;
UINTDmaSrcAddress;
PHYSICAL_ADDRESSPhysDmaDstBufferAddr;
PHYSICAL_ADDRESSPhysDmaSrcBufferAddr;
PBYTEpVirtDmaDstBufferAddr;
PBYTEpVirtDmaSrcBufferAddr;
}SPI_DMA_INFO;
typedefstruct{
PVOIDpSpiPrivate;
volatilePGPIO_REGpGPIOregs;
volatileSPI_REG*pSPIregs;
volatilePCMU_CLK_REGpSYSCONregs;
volatilePDMAC_REGpDMAC0regs;
volatilePDMAC_REGpDMAC1regs;
volatilePDMAC_REGpDMACregs;
DWORDdwRxThreadId;
DWORDdwRxThreadPrio;
HANDLEhRxEvent;
HANDLEhRxThread;
HANDLEhRxDoneEvent;
HANDLEhRxIntrDoneEvent;
DWORDdwTxThreadId;
DWORDdwTxThreadPrio;
HANDLEhTxEvent;
HANDLEhTxThread;
HANDLEhTxDoneEvent;
HANDLEhTxIntrDoneEvent;
DWORDdwSpiThreadId;
DWORDdwSpiThreadPrio;
DWORDdwSpiSysIntr;
HANDLEhSpiEvent;
HANDLEhSpiThread;
DWORDdwRxDmaDoneThreadId;
DWORDdwRxDmaDoneThreadPrio;
DWORDdwRxDmaDoneSysIntr;
HANDLEhRxDmaDoneEvent;
HANDLEhRxDmaDoneThread;
DWORDdwTxDmaDoneThreadId;
DWORDdwTxDmaDoneThreadPrio;
DWORDdwTxDmaDoneSysIntr;
HANDLEhTxDmaDoneEvent;
HANDLEhTxDmaDoneThread;
DWORDdw_spi_dma_tx_ch;
DWORDdw_spi_dma_rx_ch;
SPI_DMA_INFOSPIDMAInfo;
DWORDchnum;
BOOLm_bDVFSFixe
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