VHDL类题目.docx
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VHDL类题目.docx
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VHDL类题目
VHDL类题目:
1、三态门设计
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYtri_stateIS
PORT(din,en:
INSTD_LOGIC;
dout:
OUTSTD_LOGIC);
ENDENTITY;
ARCHITECTUREdataflowOFtri_stateIS
BEGIN
dout<=dinWHENen='1'ELSE'Z';
ENDARCHITECTURE;
2、单向总线缓冲器设计
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYbufferIS
PORT(din:
INSTD_LOGIC_VECTOR(7DOWNTO0);
en:
INSTD_LOGIC;
dout:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITY;
ARCHITECTUREbehaveOFtri_stateIS
BEGIN
PROCESS(din,en)
BEGIN
IFen='1'THENdout<=din;
ELSEdout<="ZZZZZZZZ";
ENDIF;
ENDPROCESS;
ENDARCHITECTURE;
3、4选1数据选择器
ENTITYheroIS
PORT(a,b,c,d:
INBIT;
s,r:
INBIT;
y:
OUTBIT);
ENDhero;
ARCHITECTUREbehaveOFheroIS
BEGIN
PROCESS(a,b,s,r)
BEGIN
IFs='0'andr='0'THEN
y<=a;
ELSIFs='1'andr='0'THEN
y<=b;
ELSIFs='0'andr='1'THEN
y<=c;
ELSE
y<=d;
ENDIF;
ENDPROCESS;
END;
libraryieee;
useieee.std_logic_1164.all;
entitymux4is
port(d0,d1,d2,d3:
instd_logic;
g:
instd_logic;
a:
instd_logic_vector(0to1);
y:
outstd_logic);
end;
architecturebehaveofmux4is
begin
process(a,g,d0,d1,d2,d3)
begin
ifg='0'theny<='0';
else
caseais
when"00"=>y<=d0;
when"01"=>y<=d1;
when"10"=>y<=d2;
when"11"=>y<=d3;
whenothers=>y<='0';
endcase;
endif;
endprocess;
end;
4、8-3编码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYheroIS
PORT(din:
INSTD_LOGIC_VECTOR(7DOWNTO0);
y:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));
ENDENTITY;
ARCHITECTUREbehavOFheroIS
BEGIN
PROCESS(din)
BEGIN
CASEdinIS
WHEN"00000001"=>y<="000";
WHEN"00000010"=>y<="001";
WHEN"00000100"=>y<="010";
WHEN"00001000"=>y<="011";
WHEN"00010000"=>y<="100";
WHEN"00100000"=>y<="101";
WHEN"01000000"=>y<="110";
WHEN"10000000"=>y<="111";
WHENOTHERS=>y<="000";
ENDCASE;
ENDPROCESS;
ENDARCHITECTURE;
5、3-8译码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdecoderIS
PORT(din:
INSTD_LOGIC_VECTOR(2DOWNTO0);
g1,g2,g3:
INSTD_LOGIC;
y:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITY;
ARCHITECTUREbehavOFdecoderIS
BEGIN
PROCESS(din,g1,g2,g3)
BEGIN
IFg1='0'THENy<="11111111";
ELSIFg2='1'ORg3='1'THENy<="11111111";
ELSE
CASEdinIS
WHEN"000"=>y<="11111110";
WHEN"001"=>y<="11111101";
WHEN"010"=>y<="11111011";
WHEN"011"=>y<="11110111";
WHEN"100"=>y<="11101111";
WHEN"101"=>y<="11011111";
WHEN"110"=>y<="10111111";
WHEN"111"=>y<="01111111";
WHENOTHERS=>y<="11111111";
ENDCASE;
ENDIF;
ENDPROCESS;
ENDARCHITECTURE;
6、BCD译码器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYbcdyimaIS
PORT(A:
INSTD_LOGIC_VECTOR(3DOWNTO0);
B:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDENTITY;
ARCHITECTUREbehavofbcdyimaIS
BEGIN
PROCESS(A)
BEGIN
CASEAIS
WHEN"0000"=>B<="0111111";
WHEN"0001"=>B<="0000110";
WHEN"0010"=>B<="1011011";
WHEN"0011"=>B<="1101111";
WHEN"0100"=>B<="1100110";
WHEN"0101"=>B<="1101101";
WHEN"0110"=>B<="1111101";
WHEN"0111"=>B<="0000111";
WHEN"1000"=>B<="1111111";
WHEN"1001"=>B<="1101111";
WHEN"1010"=>B<="1110111";
WHEN"1011"=>B<="1111100";
WHEN"1100"=>B<="0111001";
WHEN"1101"=>B<="1011110";
WHEN"1110"=>B<="1111001";
WHEN"1111"=>B<="1110001";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
END;
7、4位数值比较器
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYheroIS
PORT(a,b:
INSTD_LOGIC_VECTOR(3DOWNTO0);
y1,y2,y3:
OUTSTD_LOGIC);
ENDENTITY;
ARCHITECTUREbehavOFheroIS
BEGIN
PROCESS(a,b)
BEGIN
IFa>bTHENy1<='1';y2<='0';y3<='0';
ELSIFa=bTHENy1<='0';y2<='1';y3<='0';
ELSIFa ENDIF; ENDPROCESS; ENDARCHITECTURE; 8、半加器 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYh_adderIS PORT(a,b: INSTD_LOGIC; s,c: OUTSTD_logic); endentity; architecturebehavofh_adderis begin s<=axorb; c<=aandb; end; 9、RS触发器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityrsis port(s,r: instd_logic; q,qn: outstd_logic); endentity; architecturebehavofrsis signalq1,qn1: std_logic; begin q1<=snandqn1; qn1<=rnandq1; q<=q1; qn<=qn1; end; 10、D触发器 LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITYdff1IS PORT(CLK,D1: INSTD_LOGIC; Q1: OUTSTD_LOGIC); END; ARCHITECTUREbehavOFdff1IS SIGNALQQ: STD_LOGIC; BEGIN PROCESS(CLK) --VARIABLEQQ: STD_LOGIC; BEGIN IFCLK'EVENTANDCLK='1'THEN QQ<=D1; ENDIF; --Q1<=QQ; ENDPROCESS; Q1<=QQ; END; 11、4位二进制计数器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitycounteris port(clk: instd_logic; q: outstd_logic_vector(3downto0)); endentity; architecturebehavofcounteris signalq1: std_logic_vector(3downto0); begin process(clk) begin ifclk'eventandclk='1'then q1<=q1+1; endif; endprocess; q<=q1; end; 12、13进制计数器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitycnt13is port(clk: std_logic; q: outstd_logic_vector(3downto0); cout: outstd_logic); endentity; architecturebehavofcnt13is begin process(clk) variableq1: std_logic_vector(3downto0); begin ifclk'eventandclk='1'then ifq1<12thenq1: =q1+1; elseq1: =(others=>'0'); endif; endif; ifq1=12thencout<='1'; elsecout<='0'; endif; q<=q1; endprocess; end; 13、7进制计数器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entitycnt7is port(clk: instd_logic; q: outstd_logic_vector(2downto0); cout: outstd_logic); endentity; architecturebehavofcnt7is begin process(clk) variableq1: std_logic_vector(2downto0); begin ifclk'eventandclk='1'then ifq1<6thenq1: =q1+1; elseq1: =(others=>'0'); endif; endif; ifq1=6thencout<='1'; elsecout<='0'; endif; q<=q1; endprocess; end; 14、8位寄存器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityreg8_1is port(d: instd_logic_vector(7downto0);----数据输入端 ie: instd_logic;----三态控制端 clk: instd_logic;----时钟信号 q: outstd_logic_vector(7downto0));----数据输出端 end; architecturebehavofreg8_1is signalq_temp: std_logic_vector(7downto0); begin process(clk,ie) begin ifie='0'then ifclk'eventandclk='1'then q_temp<=d; endif; elseq_temp<="ZZZZZZZZ"; endif; endprocess; q<=q_temp; end; 15、8分频器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityfenpin_8is port(clk: instd_logic; div8: outstd_logic); endentity; architecturebehavoffenpin_8is signalcount: std_logic_vector(1downto0); signaltemp: std_logic; begin process(clk) begin ifclk'eventandclk='1'then ifcount="11"then temp<=nottemp; count<="00"; elsecount<=count+1; endif; endif; endprocess; div8<=temp; end; 16、10分频器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityfenpin_10is port(clk: instd_logic; div10: outstd_logic); endentity; architecturebehavoffenpin_10is signalcount: std_logic_vector(2downto0); signaltemp: std_logic; begin process(clk) begin ifclk'eventandclk='1'then ifcount="100"then temp<=nottemp; count<="000"; elsecount<=count+1; endif; endif; endprocess; div10<=temp; end; 17、5分频器 libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityfenpin_5is port(clk: instd_logic; clk_div5: outstd_logic); endentity; architecturebehavoffenpin_5is signalcount: std_logic_vector(2downto0); signaltemp1,temp2: std_logic; begin process(clk) begin ifclk'eventandclk='1'then ifcount="100"thencount<="000"; elsecount<=count+1; endif; endif; endprocess; process(count,clk) begin ifclk'eventandclk='0'then ifcount<2then temp1<='1'; elsetemp1<='0'; endif; endif; endprocess; process(count,clk) begin ifclk'eventandclk='1'then ifcount<2then temp2<='1'; elsetemp2<='0'; endif; endif; endprocess; clk_div5<=temp1ortemp2; end; LIBRARYIEEE; USEIEEE.STD_LOGIC_1164.ALL; USEIEEE.STD_LOGIC_UNSIGNED.ALL; ENTITYfenpin_5IS PORT(clk: INSTD_LOGIC; co: OUTSTD_LOGIC); END; ARCHITECTUREbehavOFfenpin_5IS SIGNALtemp: STD_LOGIC_VECTOR(2DOWNTO0); BEGIN p1: PROCESS(clk) BEGIN IF(clk'EVENTANDclk='1')THEN IF(temp="100")THEN temp<="000"; ELSEtemp<=temp+1; ENDIF; ENDIF; ENDPROCESSp1; p2: PROCESS(clk) BEGIN IF(clk'EVENTANDclk='1')THEN IF(temp="100")THEN co<='1'; elseco<='0'; ENDIF; ENDIF; ENDPROCESSp2; END; 18、F=AB+CD libraryieee; useieee.std_logic_1164.all; useieee.std_logic_unsigned.all; entityyuhuois port(a,b,c,d: instd_logic; f: outstd_logic); endentity; architecturebehavofyuhuois signalq1,q2: std_logic; begin q1<=aandb; q2<=candd; f<=q1orq2; end; 原理图设计: 19、RS触发器 20、全加器 混合设计: 21、全加器设计(自顶向下方式) 22、全加器设计(自底向上方式) libraryieee; useieee.std_logic_1164.all; entityf_adderis port(a,b,cin: instd_logic; sum,cout: outstd_logic); endentity; architecturestructoff_adderis componenth_adder port(a,b: instd_logic; s,c: outstd_logic); endcomponent; componentor_2 port(a,b: instd_logic; c: outstd_logic); endcomponent; signals1,c1,c2: std_logic; begin u1: h_adderportmap(a,b,s1,c1); u2: h_adderportmap(s1,cin,sum,c2); u3: or_2portmap(c2,c1,cout); end; libraryieee; useieee.std_logic_1164.all; entityh_adderis port(a,b: instd_logic; s,c: outstd_logic); endentity; architecturebehaveofh_adderis begin s<=axorb; c<=aandb; end; libraryieee; useieee.std_logic_1164.all; entityor_2is port(a,b: instd_logic; c: outstd_logic); endentity; architecturebehavofor_2is begin c<=aorb; end; 23、F=AB+CD(自顶向下方式) 24、F=AB+CD(自底向上方式,顶层电路采用VHDL) libraryieee; useieee.std_logic_1164.all; entityyuhuois port(a,b,c,d: instd_logic; f: outstd_logic); endentity;
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