用英文资料0615.docx
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用英文资料0615.docx
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用英文资料0615
AT89S51andMAX7219chipintroduced
AT89S51chipintroduced
TheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmel'shigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindustry-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.AT89S51pinshowninFigure1:
Figure1AT89S51pinmap
(1)themainperformanceparameters:
·.CompatiblewithMCS.-51Products
·4KBytesofIn-SystemProgrammable(ISP)FlashMemory
·1000Write/EraseCycles
·4.0Vto5.5VOperatingRange
·FullyStaticOperation:
0Hzto33MHz
·Three-levelProgramMemoryLock
·128x8-bitInternalRAM
·32ProgrammableI/OLines
·Two16-bitTimer/Counters
·SixInterruptSources
·FullDuplexUARTSerialChannel
·Low-powerIdleandPower-downModes
·InterruptRecoveryfromPower-downMode
·WatchdogTimerDualDataPointer
·Power-offFlagFastProgrammingTime
·FlexibleISPProgramming(ByteandPageMode)
(2)featuresoverview:
TheAT89S51providesthefollowingstandardfeatures:
4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo一levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.
PinFunction:
·VCC:
Supplyvoltage(allpackagesexcept42-PDIP).
·GND:
Ground(allpackagesexcept42一PDIP;for42-PDIPGNDconnectsonlythelogiccoreandtheembeddedprogrammemory).
·VDD:
Supplyvoltageforthe42-PDIPwhichconnectsonlythelogiccoreandtheembeddedprogrammemory.
·PWRVDD:
Supplyvoltageforthe42-PDIPwhichconnectsonlytheI/OPadDrivers.TheapplicationboardMUSTconnectbothVDDandPWRVDDtotheboardsupplyvoltage.
·PWRGND:
Groundforthe42一PDIPwhichconnectsonlytheI/OPadDrivers.PWRGNDandGNDareweaklyconnectedthroughthecommonsiliconsubstrate,butnotthroughanymetallink.TheapplicationboardMUSTconnectbothGNDandPWRGNDtotheboardground.
·Port0:
Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh一impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,POhasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesduringprogramverification.Externalpull-upsarerequiredduringprogramverification.
·Port1:
Port1isan8一bitbi-directionalI/Oportwithinternalpull一ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinternalpull一upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(lip)becauseoftheinternalpull-ups.
·Port2:
Port2isan8一bitbi-directionalI/Oportwithinternalpull一ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinternalpull一upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(lip)becauseoftheinternalpull一ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses.Inthisapplication,Port2usesstronginternalpull一upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogrammingandverification.
·Port3:
Port3isan8一bitbi-directionalI/Oportwithinternalpull一ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinternalpull一upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(lip)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefollowingtable.
·RST:
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.ThispindrivesHighfor98oscillatorperiodsaftertheWatchdogtimesout.TheDISRTObitinSFRAUXR(address8EH)canbeusedtodisablethisfeature.InthedefaultstateofbitDISRTO,theRESETHIGHoutfeatureisenabled.
·ALE/PROG:
AddressLatchEnable(ALE)isanoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG)duringFlashprogramming.Innormaloperation,ALEisemittedataconstantrateof1/6theoscillatorfrequencyandmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduringeachaccesstoexternaldatamemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
·PSEN:
ProgramStoreEnable(PSEN)isthereadstrobetoexternalprogrammemory.
WhentheAT89S51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.
·EA/VPP:
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingatOOOOHuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVccforinternalprogramexecutions.
Thispinalsoreceivesthe12-voltprogrammingenablevoltage(VPP)duringFlashprogramming.
·XTAL1:
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
·XTAL2:
Outputfromtheinvertingoscillatoramplifier
·SpecialFunctionRegisters:
Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.
Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.
·InterruptRegisters:
TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.
·DualDataPointerRegisters:
Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:
DPOatSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDPOandDPS=1selectsDP1.TheusershouldALWAYSinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.
·PowerOffFlag:
ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto"1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.
·MemoryOrganization:
MCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.
·ProgramMemory:
IftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S51,ifEAisconnectedtoVcc,programfetchestoaddressesOOOOHthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.
·DataMemory:
TheAT89S51implements128bytesofon-chipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.
·WatchdogTimer(One-timeEnabledwithReset-out):
TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14一bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHandOE1HinsequencetotheWDTRSTregister(SFRlocationOA6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDToverflows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.
·Timer0and1:
Timer0andTimer1isa16-bitTimer/Counter
MAX7219chipintroduced
Inoursystem,weuse8-bitserialinterfacechipMAX7219LEDdisplaydriver
toachiev
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