10第4章组合与时序逻辑的设计6.docx
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10第4章组合与时序逻辑的设计6.docx
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10第4章组合与时序逻辑的设计6
第4章组合与时序逻辑的设计
第六节存储结构
重点内容:
Registerfile
SRAM;
single-portRAM;
dual-portRAM;
ROM;
Anembeddedapplicationmayrequirestorageelementsforvariouspurposes.Nosingletypeofmemorycansatisfyallcriteria.Thereisusuallyatrade-offbetweenthesizeandperformance.
Althoughmemorymoduleshaveasimilarinternalstructure,therearemanysubtledifferencesintheirinterfaces,suchasthenumbersofreadandwriteports,clockingscheme,dataandaddressbuffering,enableandresetsignals,andinitialvalues.
AlthoughitispossibletodescribethedesiredmodulebehaviorsinHDLcode,thesynthesissoftwaremayormaynotrecognizethedesigner'sintention.Therefore,theHDLcodecannotalwaysinferthepropermemorymoduleandisnormallynotportable.
InAlteraQuartusII,therearetwomethodstoincorporateanembeddedmemorymoduleintoadesign:
1.HDLinstantiationviatheMegaWizardPlug-inManagerprogram
2.HDLinferencewithbehavioraltemplate
ThefirstoneisspecificforAlteradevicesandthesecondisasemi-device-independentbehavioraldescription.
InstantiationviaMegaWizardPlug-inManager
MegaWizardPlug-inManagerisautilityprogramtogenerateAltera-specificcomponents.ItcanbeinvokedintheQuartusIIGUIbyselectingTool>MegaWizardPlug-inManager.Adialogappearsandtheprogramguidestheuserthroughaseriesofquestionsandthengeneratesseveralfiles.Thefilewiththe.qipextensionisatextfilethatcontainstheinformationaboutthecore.Thefilewiththe.vhdextensioncontainstheinstantiatedcomponentandwrappingcode.
HDLinferencewithbehavioraltemplate
Althoughitisnotpossibletodevelopadevice-independentHDLdescription,theQuartusIImanualsuggestsacollectionofbehavioralHDLtemplatestoinfermemorymodulesforAlteraFPGAdevices.Thesetemplatesaredonebybehavioraldescriptionsandcontainnodevice-specificcomponentinstantiation.TheyareeasytounderstandandcanbesimulatedwithoutanadditionalHDLlibrary.However,whilethedescriptiondoesnotexplicitlyrefertoanyAlteracomponent,thecodemaynotberecognizedbyotherthird-partysynthesissoftwareandthedesiredmemorymodulecannotalwaysbeinferred.Thus,thesetemplatescanbestbedescribedas"semi-portable"and"semi-device-independent"behavioraldescriptions.Becauseoftheclarityofthebehavioraldescription,weusethismethodinthissection.
Templatesforcommonlyusedmemorymodules,includingasynchronoussingle-portRAM,asynchronousread-writedual-portRAM,andaROM,arediscussedinthefollowingsubsections.
1、Registerfile
Aregisterfileisacollectionofregisterswithoneinputportandoneormoreoutputports.Theregisterfileisgenerallyusedasfast,temporarystorage.
Thewriteaddresssignal,w_addr,specifieswheretostoredata,andthereadaddresssignal,r_addr,specifieswheretoretrievedata.
Theconceptualdiagramofa4-by-8(i.e.,fourwordsand8bitsperword)registerfileisshownFigure1.Thedesignconsistsoffourregisterswithenablesignals,awritedecodingcircuit,andreadmultiplexingcircuits.
Figure1four-wordregisterfile.
Thewritedecodingcircuitexaminesthewr_ensignalanddecodesthewriteportaddress.Ifthewr_ensignalisasserted,thedecodingcircuitfunctionsasabinarydecoderthatassertsoneofthefourensignalsofthecorrespondingregister.Thew_datasignalwillbestoredintothecorrespondingregisterattherisingedgeoftheclock.Thereadmultiplexingcircuitconsistsofa4-to-lmultiplexer.Itutilizesr_addrastheselectionsignaltoroutethedesiredregisteroutputtothereadport.
First,sincenobuilt-intwo-dimensionalarrayisdefinedinthestd_logic_1164package,auser-definedarray-of-arraydatatype,reg_file_type,isintroduced.Itisfirstdefinedbyatypestatementandisthenusedbythearray_regsignal.
Notethattheregistersarestructuredasatwo-dimensional4-by-8arrayofDFFsandwouldbestberepresentedbyatwodimensionaldatatype.Thuswemustcreateauser-defineddatatype.AssumethatthereareADDR_WIDTHbitsintheaddress(i.e.,2ADDR_WIDTHwords)andthereareDATA_WIDTHbitsperword.Thenewdatatypecanbedefinedinatypestatement
typemem_2d_typeisarray(0to2**ADDR_WIDTH-1)ofstd_logic_vector(DATA_WIDTH-1downto0);
andthenused,asin
signalarray_reg:
mem_2d_type;
Wecanderivethecodefollowingtheconceptualdiagram,asshowninfollowing.
Listing1:
libraryieee;
useieee.std_logic_1164.all;
entityreg_file_4x8is
port(clk:
instd_logic;
wr_en:
instd_logic;
w_addr,r_addr:
instd_logic_vector
(1downto0);
w_data:
instd_logic_vector(7downto0);
r_data:
outstd_logic_vector(7downto0));
endreg_file_4x8;
architecturearchofreg_file_4x8is
constantADDR_WIDTH:
natural:
=2;
constantDATA_WIDTH:
natural:
=8;
typemem_2d_typeis
array(0to2**ADDR_WIDTH-1)ofstd_logic_vector(DATA_WIDTH-1downto0);
signalarray_reg:
mem_2d_type;
signalen:
std_logic_vector(2**ADDR_WIDTH-1downto0);
begin
--4registers
p1:
process(clk)
begin
if(clk'eventandclk='1')then
ifen(3)='1'then
array_reg(3)<=w_data;
endif;
ifen
(2)='1'then
array_reg
(2)<=w_data;
endif;
ifen
(1)='1'then
array_reg
(1)<=w_data;
endif;
ifen(0)='1'then
array_reg(0)<=w_data;
endif;
endif;
endprocess;
--decodinglogicforwrit2address
p2:
process(wr_en,w_addr)
begin
if(wr_en='0')thenen<=(others=>'0');
else
casew_addris
when"00"=>en<="0001";
when"01"=>en<="0010";
when"10"=>en<="0100";
whenothers=>en<="1000";
endcase;
endif;
endprocess;
--readmultiplexing
withr_addrselect
r_data<=array_reg(0)when"00",
array_reg
(1)when"01",
array_reg
(2)when"10",
array_reg(3)whenothers;
endexplicit_arch;
Itconsistsofacollectionoffourregisters,adecodinglogictogeneratetheenablesignals,andamultiplexertoroutethedesireddatatothereadport.Wecanduplicatethedecodinglogicandmultiplexinglogicifadditionalwriteportsorreadportsareneeded.
Althoughthecodeisstraightforward,thedecodingandmultiplexingstatementsbecomecumbersomeasthesizeoftheregisterfileincreases.Analternativemethodistousedynamicindexing,inwhichasignalisusedasanindextoaccessanelementinthearray.ThecodeforaparameterizedregisterfileisshowninListing2.Twogenericsaredefinedinthisdesign.TheDATA_WIDTHgenericspecifiesthenumberofbitsinawordandtheADDR_WIDTHgenericspecifiesthenumberofaddressbits,whichimpliesthatthereare2ADDR_WIDTHwordsinthefile.
Listing2Parameterizedregisterfile
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entityreg_fileis
generic(ADDR_WIDTH:
integer:
=2;DATA_WIDTH:
integer:
=8);
port(clk:
instd_logic;
wr_en:
instd_logic;
w_addr:
in
std_logic_vector(ADDR_WIDTH-1downto0);
r_addr:
in
std_logic_vector(ADDR_WIDTH-1downto0);
w_data:
in
std_logic_vector(DATA_WIDTH-1downto0);
r_data:
out
std_logic_vector(DATA_WIDTH-1downto0)
);
endreg_file;
architecturearchofreg_fileis
typemem_2d_typeisarray(0to2**ADDR_WIDTH-1)ofstd_logic_vector(DATA_WIDTH-1downto0);
signalarray_reg:
mem_2d_type;
begin
process(clk)
begin
if(clk'eventandclk='1')then
ifwr_en='1'then
array_reg(to_integer(unsigned(w_addr)))<=w_data;
endif;
endif;
endprocess;
--readport
r_data<=array_reg(to_integer(unsigned(r_addr)));
endarch;
Notethatthearray_reg(…w_addr…)<=…and…<=array_reg(…r_addr…)statementsinferdecodingandmultiplexinglogic,respectively.Althoughthedescriptionismoreabstract,Alterasoftwarerecognizesthislanguageconstructandcanderivethecorrectimplementationaccordingly.
2、SRAM
AregisterfilecanbeconsideredasastoragecomponentinwhichtheDFFsconstitutethebasicmemorycells.SinceallDFFsaredrivenbythesameclocksignal,theoperationsynchronous.TheSRAM(staticrandomaccessmemory)organizationissimilartothatofaregisterfileexceptthattheDFFsarereplacedwiththeDlatches.Sincethereisnoclock,itsoperationisasynchronous.TheHDLdescriptionforagenericSRAMissimilartothatofaregisterfilebutwithouttheclock,asshowninListing3.
Listing3
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entityasync_sramis
generic(ADDR_WIDTH:
integer:
=2;
DATA_WIDTH:
integer:
=8);
port(wr_en:
instd_logic;
w_addr:
instd_logic_vector
(ADDR_WIDTH-1downto0);
r_addr:
instd_logic_vector
(ADDR_WIDTH-1downto0);
d:
instd_logic_vector
(DATA_WIDTH-1downto0);
q:
outstd_logic_vector
(DATA_WIDTH-1downto0)
);
endasync_sram;
architecturenot_use_archofasync_sramis
typemem_2d_typeisarray
(2**ADDR_WIDTH-1downto0)
ofstd_logic_vector(DATA_WIDTH-1downto0);
signalarray_reg:
mem_2d_type;
begin
p1:
process(wr_en,w_addr,d)
begin
ifwr_en='1'then
array_reg(to_integer(unsigned(w_addr)))<=d;
endif;
endprocess;
q<=array_reg(to_integer(unsigned(r_addr)));
endnot_use_arch;
Atthetransistorlevel,theareausedtoconstructalatchismuchsmallerthanthatofaDFF.However,sincethereisnoinherentstructureintheCycloneIIdeviceresemblingasynchronousSRAM,itissynthesizedfromscratchusingafeedbackcircuitwithLEs.Theimplementationisinefficientandfrequentlyleadstodifficulttimingproblems.Thus,usingFPGA'sinternalresourceforasynchronousSRAMshouldbeavoidedandthecodeisjustfordemonstrationpurposes.
3、single-p
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