SoC设计方法与实现第十一章-低功耗-OK.ppt
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SoC设计方法与实现第十一章-低功耗-OK.ppt
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SoC设计方法与实现设计方法与实现郭炜郭炜郭筝郭筝谢憬谢憬第十一章第十一章低功耗设计低功耗设计OutlineOutlineWhylowpowerWhylowpowerSourcesofpowerconsumptionSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowerdesignmethodologyLowpowertechniquesLowpowertechniquesPoweranalysisandtoolsPoweranalysisandtoolsTrendsinthefutureTrendsinthefuture2024/2/102WhyLowPowerWhyLowPowerPotablesystem-BatterylifetimenExample:
mobilephone,PDA,DigitalcameraDesktops:
highpowerconsumptionnReliabilityandperformancenNeedexpensivechippackage,coolingsystemSeveraldeleteriouseffectsnDecreasedreliabilityandperformancenIncreasedcost:
packagingcostandcoolingsystemnExceedpowerlimitsofthechip&system2024/2/103Power,CostandHeatComponent:
siliconandpackagenIncreaseddiesize(widerpowerbusses)nNeedbetterthermalcapabilities(packagematerial)nNeedbetterelectricalcapabilitiesSystem:
CoolingandmechanicalsnLargerfansnOversizedpowersuppliesPowerlimitstothewalln1100Wdclimitfor110V/20Aplug2024/2/104ChallengeofDesignasProcessScalingChallengeofDesignasProcessScaling2024/2/105OutlineOutlineWhylowpowerWhylowpowerSourcesofpowerconsumptionSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowerdesignmethodologyLowpowertechniquesLowpowertechniquesPoweranalysisandtoolsPoweranalysisandtoolsTrendsinthefutureTrendsinthefuture2024/2/106SourceofPowerConsumptionDynamicpowerconsumptionDynamicpowerconsumptionStaticpowerconsumptionStaticpowerconsumptionKeyareasofpowerconsumptioninSOCKeyareasofpowerconsumptioninSOC2024/2/107SourceofPowerDissipationinCMOSDevicesC=nodecapacitancesC=nodecapacitancesNNswsw=switchingactivities=switchingactivities(numberofgatetransitions(numberofgatetransitionsperclockcycle)perclockcycle)F=frequencyofoperationF=frequencyofoperationVVDDDD=supplyvoltage=supplyvoltageQQscsc=chargecarriedby=chargecarriedbyshortcircuitcurrentshortcircuitcurrentpertransitionpertransitionIIleakleak=leakagecurrent=leakagecurrent2024/2/108StaticPowerConsumption:
StaticPowerConsumption:
Leakagecurrents:
nSub-thresholdcurrent(I22)nGateleakagenGatetunnelling(I44)nGateinduceddrainleakage(I33)npn-junctionreversecurrent(I11)DCcurrentsnAnalogcircuit:
sense-amps,pull-upsnStatedependent2024/2/109Leakagevs.ProcessLeakagevs.ProcessWhatwillbethedominatedleakagecurrent?
Whatwillbethedominatedleakagecurrent?
LongChannel(L1um)VerysmallleakageShortchannel(L180nm,tox30A)SubthresholdleakageVeryshortchannel(L90nm,tox20A)subthreshold+gateleakageNano-scaled(L90nm,Tox20A)Subthreshold+gate+junctionleakageSub-thresholdleakagecurrentHasbecomequiteimportantwithtechnologyscalingGateleakagecurrentIsbecomingimportantwithshrinkingdevicedimensionsPNjunctionleakagecurrentNegligible2024/2/1010OutlineOutlineWhylowpowerWhylowpowerSourcesofpowerconsumptionSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowerdesignmethodologyLowpowertechniquesLowpowertechniquesLowpoweranalysisandtoolsLowpoweranalysisandtoolsTrendsinthefutureTrendsinthefuture2024/2/1011LowPowerDesignMethodologyMustknowyoursystemMustknowyoursystemMaximizetheperformancewhileminimizethepowerMaximizetheperformancewhileminimizethepowerconsumptionconsumptionMinimizethepowerconsumptionwhilemaximizetheMinimizethepowerconsumptionwhilemaximizetheperformanceperformance2024/2/1012OpportunitiesforPowerSaving2024/2/1013OutlineOutlineWhylowpowerWhylowpowerSourcesofpowerconsumptionSourcesofpowerconsumptionLowpowerdesignmethodologyLowpowerdesignmethodologyLowpowertechniquesLowpowertechniquesPoweranalysisandtoolsPoweranalysisandtoolsTrendsinthefutureTrendsinthefuture2024/2/1014LowPowerTechniquesLowPowerTechniquesLeakagepowercontrolLeakagepowercontrolDynamicpowercontrolDynamicpowercontrolArchitecturelevelpoweroptimizationArchitecturelevelpoweroptimizationSystemlevelpoweroptimizationSystemlevelpoweroptimization2024/2/1015LowPowerTechniquesProcessscalingProcessscalingnLowVdd,Multi-thresholdVoltagescalingVoltagescalingnSubstratebias(200mv)nMulti-voltage(voltageisland)nDynamicvoltagescaling;multi-thresholdHWdesigntechniquesHWdesigntechniquesnPre-computation,glitchminimization,Logiclevel,PhysicalleveloptimizationLowpowerSystem/SWLowpowerSystem/SWnPowerawareOperationSystem,compiler,SWdesignetc.2024/2/1016LowPowerTechniquesonChipDesignLowPowerTechniquesonChipDesignLeakagePowerLeakagePowernMultiVtoptimizationnPowergatingnSubstratebiasnPowergatingDynamicPowerDynamicPowernMulti-voltagedesignnAdvancedclock-gatingnGate-levelpoweroptimization2024/2/1017TechniquesforReduceLeakagePowerTechniquesforReduceLeakagePower2024/2/1018UsingMulti-VtLibrariesUsingMulti-VtLibrariesTimingandleakagetradeoffTimingandleakagetradeoffnLowVtcell:
fasterspeed,highleakagenHighVtcell:
slowerspeed,lowerleakagenPrinciple:
lowVtforcriticalpathandhighVtfornon-criticalpathsHighVtcellonCriticalPathHints:
1.YouneedtohavedualVtlibrary2.Youneedtopayfortheextralayermaskformulti-vt2024/2/1019UsingMulti-VtLibrariescont.SynthesisStrategy:
SynthesisStrategy:
nUsehighVtcellsfirst,thenfixsetupviolationbyreplacethehighVtcellsonthecriticalpathtolowVtcellsnUselowVtcellsfirst,thenswaptohighVtcells,fixsetupviolationbyswaplowVtcellsonthepathsNoareapenaltyNoareapenaltynLibrarydesignforfreelymixandmatchonSoCdesign2024/2/1020PowerGatingAlsocalledMulti-ThresholdCMOS(MTCOMS),AlsocalledMulti-ThresholdCMOS(MTCOMS),logicsleepcontrol,etc.logicsleepcontrol,etc.Activemode:
sleepcontroldeviceson,VDDVandActivemode:
sleepcontroldeviceson,VDDVandGNDVactasvirtualsupplyGNDVactasvirtualsupplySleepmode:
sleepcontroldevicesoff,reduceSleepmode:
sleepcontroldevicesoff,reduceleakageleakagenHighVttransistorsreducingbothleakageandswitchingpower2024/2/1021PowerGatingcont.SleeptransistorsusedonlyonthesupplyrailoronbothSleeptransistorsusedonlyonthesupplyrailoronbothsupplyandgroundrailssupplyandgroundrailsnNotaddedoneverygatePowergatingretentionregisterPowergatingretentionregisternActivemodenHighperformanceregularFFfunctionnSleepModenCut-offVddnLowleakagestagesavinglatchfunction2024/2/1022BodyBiasVariablethresholdaccordingtobodybiasingVariablethresholdaccordingtobodybiasingZerobodybiasinactivemode(LowVZerobodybiasinactivemode(LowVt)Reversebodybiasinstand-bymode(HighVReversebodybiasinstand-bymode(HighVt)Tradeoffbetweenthetimeonmoduleturn-onandleakagecurrentTradeoffbetweenthetimeonmoduleturn-onandleakagecurrentTriplewellstructureCMOSInverterHint:
Doyouhavethetriplewellstructuredstandardcelllib?
2024/2/1023TechniquesforReduceDynamicPowerTechniquesforReduceDynamicPower2024/2/1024MultiVoltageDesignBlockbasedapproachinthedesignflowBlockbasedapproachinthedesignflowNeedtoadditionalisolationcellsandvoltagelevel-shiftercellsNeedtoadditionalisolationcellsandvoltagelevel-shiftercellsbetweenvoltagedomainsbetweenvoltagedomains2024/2/1025ClockGatingTechnologyTogglingconsumepower.Enablethemoduleclockonlywhenneededgated_clkEnableLogicGlobalClkComb.LogicDataReg2024/2/1026ClockGatingCellDesignProblemwithsimpleclockgating:
Problemwithsimpleclockgating:
nUncompletedcyclenGlitch2024/2/1027ClockGatingwithLatchAddatransparent-lowlatchMakesuretheclkgatingcellsareplacedtightlyforcorrectfunctionclkcellhardeningCommonlyinSoC:
makea“hardmacro”-clkgatingcellRTLcodeforclkcell:
always(clkorclk_en)if(!
clk)ctrl_latch=clk_en;assigngclk=ctrl_latch&clkClockgatingcellsandaglitchfreeclockgating2024/2/1028ClockGatingWithIntegratedTestLogicAbilitytoletclkpassthroughintestmodeAbilitytoletclkpassthroughintestmode(TEST=1)(TEST=1)2024/2/1029GatedClockinClockTreeDesignDisableclockingneartherootofaclocktree,insteadofatDisableclockingneartherootofaclocktree,insteadofateachFF.eachFF.SpecialcaremustbetakeninclktreesynthesistopreventtheSpecialcaremustbetakeninclktreesynthesistopreventthebuffersinsertedbetweenclkrootandtheclkgatingcellbuffersinsertedbetweenclkrootandtheclkgatingcell2024/2/1030GateLevelOptimizationGateLevelOptimizationTechnologyindependentoptimization:
Technologyindependentoptimization:
nCircuitoptimization:
logicoptimization,reduceredundantlogicnTrimmingforlowpower:
reducepositiveslackreducepositiveslacknGateresizingnPinswapping/reassignmentnRe-mappingnPhaseassignmentnRe-factoringLowpowerdriventechnologymappingLowpowerdriventechnologymappingnlowpowercell2024/2/1031GateLevelOptimizationGateSizingGatesizingGatesizingnDown-sizegatesonfastpathstodecreasetheirinputcapacitancesforminimizingswitchingcurrentinfrontdrivernEnlargeheavilyloadedgatestoincreasetheiroutputslewratesforminimizingshort-circuitcurrent2024/2/1032DealingwithGlitchesForsometypeofdatapathcircuits,upto60%oftheForsometypeofdatapathcircuits,upto60%ofthedynamicpowerisduetoglitchesdynamicpowerisduetoglitchesVeryexpensivecalculationVeryexpensivecalculationnNeedtopropagateprobabilisticwaveforms2024/2/1033Example:
GlitchMinimizationHazardoustransitionoccursattheoutputofANDgateduetoHazardoustransitionoccursattheoutputofANDgateduetodifferentdelaysthroughtwodifferentdelaypathsconvergingatdifferentdelaysthroughtwodifferentdelaypathsconvergingattheinputstothegatetheinputstothegate2024/2/1034PhysicalLevelOptimizationLibraryDesign:
Energy-efficientcellsLibraryDesign:
Energy-efficientcellsDesignplanning
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