CPU design.docx
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CPU design.docx
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CPUdesign
CPUSystemDesign
Purpose
ThepurposeofthisprojectistodesignasimpleCPU.ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogram.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.weonlyneedconsiderthefollowingitems:
Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.
Tasks
CPUOrganization
FetchInstructions:
TheCPUmustreadinstructionsfrommemory
InterpretInstructions:
Theinstructionmustbedecodedtodeterminewhatactionisrequired.
FetchData:
TheexecutionofaninstructionmayrequirereadingdatafrommemoryorI/Omodules.
ProcessData:
Theexecutionofaninstructionmayrequireperformingsomearithmeticorlogicoperationondata.
WriteData:
TheresultsofanexecutionmayrequiringwritingdatatomemoryoranI/Omodule
InternalRegistersandMemory
MAR(MemoryAddressRegister)containsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.
MBR(MemoryBufferRegister)containsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.
PC(ProgramCounter)keepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.
IR(InstructionRegister)containstheopcodepartofaninstruction.Inourdesign,IRhas8bits.
BR(BufferRegister)isusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.
ACC(Accumulator)holdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.
MR(MultiplierRegister)isusedforimplementingtheMPYinstruction,holdingthemultiplieratthebeginningoftheinstruction.Whentheinstructionisexecuted,itholdspartoftheproduct.
DR(DivisionRegister)isusedforimplementingtheDIVinstruction,youcandefineitaccordingtoyourdivisionalgorithm.
LPM_RAM_DQisaRAMwithseparateinputandoutputports,itworksasmemory,anditssizeis256×16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandtesttheperformanceofCPU.
ALU(ArithmeticLogicUnit)isacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows
CPUDesign
YoushoulddeterminethecontrolsignalsaccordingtotheCPUarchitectureandyourdesign.Anexampleisgivenbelowtoshowtheprocedure,thisexampledescribesthecontrolunitdesignfortheLOADinstruction.
TheoverallconnectionofthesimulatedprinterandPOCexpressedinthetopmoduleform
ctl
thecontrolsignalfromCUtoalltheregisters
reset
asignaltoresetCPU
clk
clocksignal
Thesignalfromoneelementtoeachotherisdefinedasfollowed:
MBR
Signals
functions
IN
ACCMBR[15..0]
receivethedatafromACC
PC[7..0]
receivetheinstructionaddressfromPC
BRMBR[15..0]
receivethedatafromBR
RAMin[15..0]
receivethedatafromRAM
OUT
RAMout
sendthedatatoRAM
MBR
sendthedatatoBR,PC,MARandIR
WR
asignaltoRAMtodeterminereadingorwriting
MAR
Signals
functions
IN
MBR[15..0]
receivetheaddressofdatafromMBR
PC[7..0]
receivetheaddressofinstructionfromPC
SSMAR[7..0]
receivetheaddressofstack
OUT
RAMadd[7..0]
sendtheaddresstoRAM
PC
Signals
functions
IN
MBR[15..0]
receivetheaddressofnextinstructionfromMBR
OUT
PC[7..0]
sendtheaddressofinstructiontoMAR
IR
Signals
functions
IN
MBR[15..0]
receiveinstructionsfromMBR
OUT
IR[7..0]
sendinstructionstoCU
BR
Signals
functions
IN
MBR[15..0]
receivedatafromMBR
OUT
BR[15..0]
senddatatoACCandALU
BRMBR[15..0]
senddatatoMBR
ACC
Signals
functions
IN
ALUACC[15..0]
receivedatafromALU
BR[15..0]
receivedatafromBR
OUT
ACC[15..0]
senddatatoACC
ACCMBR[15..0]
senddatatoMBR
CU
Signals
functions
IN
IR[7..0]
receiveinstructionsfromBR
flagsCU[7..0]
receiveflagsfromFlags
s
asignalfromALUtoproceedCU
OUT
ROM[4..0]
sendtheaddressofM-instructioninROM
ALUctl[3..0]
acontrolsignaltoALUtodeterminetheoperate
Thesimplemicro-instructionsetinROMisdesignedasfollowed:
Micro-I
NUM(HEX)
Meanings
c0
·0000
nooperation
c1
·0001
MBR<-PC
c2
·0002
MAR<-PC
c3
·0004
PC<-MBR
c4
·0008
IR<-MBR;BR<-MBR
c5
·0010
MBR<-RAM
c6
·0020
ALU<-BR
c7
·0040
ALU<-ACC
c8
·0080
MAR<-MBR
c9
·0100
ACC<-ALU
c10
·0200
ACC<-BR
c11
·0400
MBR<-ACC
c12
·0800
RAM<-MBR
c13
·1000
PC<-PC+1
c14
·2000
MBR<-BR
c15
·4000
MAR<-SS
c16
·8000
SS<-SS+1
Flags
Signals
functions
IN
ALUflags[7..0]
receiveflagsfromALU
OUT
flagsALU[7..0]
sendflagstoALU
flagsCU[7..0]
sendflagstoCU
Theeachbitofflagsisdesignedasfollowed:
Flags
0
CF
whenneedcarry->1
1
BF
whenneedborrow->1
2
PF
whenshiftACC->0/1
3
ZF
whenanswer=0->1
4
OF
whenoverflow->1
5
SF*
whenanswerisnegative->1
6
IF*
whendisableinterupt->1
7
/
Notes:
‘*’meansdoesn’tuseinthisdesign.‘/’meanshasnodefinition.Thesameasfollowed.
SS
Signals
functions
OUT
SSMAR[7..0]
sendtheaddressofstacktoMAR
ALU
Signals
functions
IN
BR[15..0]
receivedatafromBR
ACC[15..0]
receivedatafromACC
ALUctl[3..0]
acontrolsignalformCUtodeterminetheoperate
flagsALU[7..0]
receiveflagsfromflags
OUT
ALUACC[15..0]
sendtheanswertoACC
ALUflags[7..0]
sendflagstoflags
s
asignaltoproceedCU
ThecontrolsignalfromCUtoALUisdesignedasfollowed:
ALU
NUM(binary)
Functions
ADD
·0100
plus
ADC
·0101
pluswithflags
SUB
·0110
subtract
SBB
·0111
subtractwithflags
AND
·1000
and
OR
·1001
or
NOT
·1010
not
XOR
·1011
xor
SHL
·1100
shiftACCtoleft1bit
SHR
·1101
shiftACCtoright1bit
SRL
·1110
shiftACCtoleft1bit,logic
SRR
·1111
shiftACCtoright1bit,logic
MPY
·0010
MPY
DIV
·0011
DIV
Asimpleinstructionsetisdesignedasfollowed:
Instruction
Control
(765432)
MicroOpcode(c)
FetchIandD(10)
直接
间接
无
·01
·10
·00
LOADX
·000010
410
/
STOREX
·000011
1112
/
ADDX
·001000
467N9
/
SUBX
·001010
467N9
/
ANDX
·001100
467N9
/
ORX
·001101
467N9
/
NOTX
·001110
467N9
XORX
·001111
467N9
/
SRL
·011000
7N9
/
/
SRR
·011010
7N9
/
/
·
ADCX
·001001
467N9
/
SBBX
·001011
467N9
/
SHL
·011001
7N9
/
/
SHR
·011011
7N9
/
/
·
MPYX
·010100
467N9
/
DIVX
·010101
467N9
/
JMPGEZX
·010001
32
/
JMPX
·010000
32
/
·
HALT
·000000
/
/
/
CALLX
·100000
11512143
/
RET
·100001
161553
/
/
PUSH
·100010
151112
/
/
POP
·100011
16155410
/
/
Simulationresults
TheprogramintheRAMiswrittenbeforehandonthebaseofinstructionset.
Program
CALLCAL
LOADA4
MPYA4
PUSH
DIVA8
POP
HALT
CAL:
LOAD10
STOREA4
LOADA2
STOREA3
LOOP:
LOADA4
ADDA3
STOREA4
LOADA3
SUBA1
STOREA3
JMPGEZLOOP
RET
Thesimulationresultisdisplayasthenextfigure.
Figure1:
TheanswerofplusfromonetoahundrediswrittentoRAM
Figure2:
Thefirststepoftheprogram“CALL50”
Figure3:
Begintocalculateplusfromonetoahundred
Figure4:
Calculating13BAmultiply13BA
Figure5:
Calculating13BAdivide0008
Figure6:
HALTandwaitforaresetsignal
ConclusionsandDiscussions:
1.IsthePOCyoudesigninaccordwiththetheory?
Yes,mydesignofCPUcanshowthebasicfunctionofarealCPUandsimulateawholeprogram.
2.Arethereanyplacesyoucanrevisetoimproveyourdesign?
Toimprovemydesign,IcanoptimizethedesignofALU.Intheresentdesign,therearesometemporaryregistersintheALU.However,itshouldbeasimplelogicelectriccircuit.Therefore,IcanrevisetoimprovemydesignbydesigningtheALUagain.
3.Whatarethecharacterizationsofyourdesign?
ThecharacterizationofmydesigncanbeconcludedasdesigningaoverallconnectionfirstanduseVHDLtofillineachelement.TheelementofCUisthemostimportantpartofthewholeprojectanddeterminingthemicrocontrolinstructionisthefirstworktofinishbyme.
4.Whatdoyoulearnfromthisdesign?
IlearnedhowtodesignaprojectandthegrammarofVHDL.Ofcourse,IamfamiliarwithasimpleprocessofaCPU,understandinghowaCPUfetchinstructionsandexecutethemconcludingADD,SUB,JMPandsoon.
Appendix
MBR
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityMBRis
port(
ACC_in:
instd_logic_vector(15downto0);
PC_in:
instd_logic_vector(7downto0);
BR_in:
instd_logic_vector(15downto0);
RAM_out:
outstd_logic_vector(15downto0);
RAM_in:
instd_logic_vector(15downto0);
MBR_out:
outstd_logic_vector(15downto0);
ctl:
instd_logic_vector(15downto0);
WR:
outstd_logic;
reset:
instd_logic;
clk:
instd_logic
);
endMBR;
architecturefunction_MBRofMBRis
begin
process(clk)
variableMBR_t:
std_logic_vector(15downto0);
variableRAM_t:
std_logic_vector(15downto0);
variablex:
integerrange0to1;
begin
if(clk='1'andclk'event)then
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