杭电计组实验10实现RIJ型指令的CPU设计实验Word格式文档下载.docx
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杭电计组实验10实现RIJ型指令的CPU设计实验Word格式文档下载.docx
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clk=0;
//Wait100nsforglobalresettofinish#100;
//Addstimulushere
forever
begin
#2;
clk=~clk;
#10;
clk_100MHz=~clk_100MHz;
end
endmodule
顶层LED验证模块
moduleTOP_LED(clk_100MHz,oclk,rst,SW丄ED);
inputclk_100MHz;
inputoclk,rst;
input[3:
0]SW;
outputreg[7:
0]LED;
wirerclk;
wireZF,OF;
0]F;
0]M_R_Data;
0]PC;
xiaodoudoudong(clk_100MHz,oclk,rclk);
TOP_RIJ_CPU(rst,clk_100MHz,rclk,ZF,OF,F,M_R_Data,PC);
always@(*)
case(SW)
4'
b0000:
LED二F[7:
0];
b0001:
LED二F[15:
8];
b0010:
LED=F[23:
16];
b0011:
LED=F[31:
24];
b0100:
LED=M_R_Data[7:
b0101:
LED=M_R_Data[15:
b0110:
LED二M_R_Data[23:
b0111:
LED=M_R_Data[31:
b1000:
beginLED[7:
2]=0;
LED[1]=OF;
LED[0]=ZF;
end
b1100:
LED=PC[7:
b1101:
LED=PC[15:
b1110:
LED=PC[23:
b1111:
LED=PC[31:
default:
LED=0;
endcase
顶层RIJ型指令CPU验证模块:
moduleTOPRIJCPU(inputrst,inputelk100MHz,inputclk,outputZF,outputOF,output[31:
0]F,output[31:
0]M_R_Data,output[31:
0]PC);
wireWrite_Reg;
0]lnst_code;
wire[4:
0]rs;
0]rt;
0]rd;
0]rs_data;
0]rt_data;
0]rd_data;
0]imm_data;
〃被扩展的立即数
wire[15:
0]imm;
//wirerd_rt_s;
wire[1:
0]w_r_s;
wireimm_s;
〃判断是否需要扩展
wirert_imm_s;
//B端选择rt或者是扩展后的imm
wireMem_Write;
//wirealu_mem_s;
wire[1:
0]wr_data_s;
0]W_Addr;
0]W_Data;
0]R_Data_A;
0]R_Data_B;
0]ALU_B;
//B端口数据
wire[2:
0]ALU_OP;
0]PC_s;
0]PC_new;
wire[25:
0]address;
pcpc_connect(clk,rst,PC_s,R_Data_A,imm_data,address,lnst_code,PC);
OP_YIMAop(Inst_code,ALU_QP;
rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF);
assignW_Addr=(w_r_s[1])?
5'
b11111:
((w_r_s[0])?
rt:
rd);
assignimm_data=(imm_s)?
{{16{imm[15]}},imm}:
{{16{1'
b0}},imm};
Register_fileR_connect(rs,rt,W_Addr,Write_Reg,W_Data,clk,rst,R_Data_A,R_Data_B);
assignALU_B=(rt_imm_s)?
imm_data:
R_Data_B;
ALUALU_connect(R_Data_A,ALU_B,F,ALU_ZFOF);
RAM_BData_Mem(
.clka(clk_100MHz),//inputclka
.wea(Mem_Write),//input[0:
0]wea
.addra(F[5:
0]),//input[5:
0]addra
.dina(R_Data_B),//input[31:
0]dina
.douta(M_R_Data)//output[31:
0]douta
);
assignW_Data=(wr_data_s[1])?
PC_new:
((wr_data_s[O])?
M_R_Data:
F);
PC取指令模块:
modulepc(inputclk,inputrst,input[1:
0]PC_s,input[31:
0]R_Data_A,
input[31:
0]imm_data,input[25:
0]address,output[31:
0]lnst_code,output[31:
reg[31:
wire[31:
initial
PC<
=32'
h00000000;
Inst_ROMInst_ROM1(
.clka(clk),
.addra(PC[7:
2]),
.douta(Inst_code)
assignPC_new=PC+4;
always@(negedgeclkorposedgerst)
if(rst)
else
begincase(PC_s)
2'
b00:
二PC_new;
bO1:
二R_Data_A;
b10:
=PC_new+(imm_data<
<
2);
b11:
={PC_new[31:
28],address,2'
b00};
OP指令功能译码模块:
moduleOP_YIMA(inst,ALU_OPfe,rt,rd,Write_Reg,imm,imm_s,rt_imm_s,Mem_Write,address,w_r_s,wr_data_s,PC_s,ZF)input[31:
0]inst;
outputreg[2:
outputreg[4:
outputregWrite_Reg;
outputreg[15:
//outputregrd_rt_s;
outputregimm_s;
outputregrt_imm_s;
outputregMem_Write;
outputreg[25:
outputreg[1:
0]w_r_s;
0]wr_data_s;
0]PC_s;
inputZF;
//处理R型指令
if(inst[31:
26]==6'
b000000)
rd=inst[15:
11];
rt=inst[20:
rs=inst[25:
21];
〃alu_mem_s=O;
wr_data_s=2'
b00;
Mem_Write=O;
〃rd_rt_s=O;
w_r_s=2'
rt_imm_s=0;
case(inst[5:
0])
6'
b100000:
beginALU_OP=3'
b100;
Write_Reg=1;
PC_s=2'
end6'
b100010:
b101;
b100100:
bOOO;
bOO;
b100101:
b001;
b100110:
b010;
b100111:
b011;
b101011:
b110;
b000100:
b111;
b001000:
Write_Reg=0;
b01;
endendcaseend
//1型立即数寻址指令——
29]==3'
b001)
imm=inst[15:
Mem_Write=0;
〃rd_rt_s=1;
rt_imm_s=1;
〃alumems=0;
w_r_s=2'
case(inst[31:
26])
beginimm_s=1;
ALU_OP=3'
b001100:
beginimm_s=0;
b000;
b001110:
b001011:
//处理I型取数/存数指令------
if((inst[31:
30]==2'
b10)&
&
(inst[28:
26]==3'
b011))
rt=inst[20:
//rt寄存器
rs=inst[25:
//rs寄存器
//rd_rt_s=1;
//rt作为目的存储器rt_imm_s=1;
//imm作为源操作数imm_s=1;
wr_data_s=2'
b100011:
beginMem_Write=O;
Write_Reg=1;
beginMem_Write=1;
Write_Reg=0;
endendcase
//处理I型跳转指令
27]==5'
b00010)
//rt
rs=inst[25:
//rs
beginrt_imm_s=0;
Mem_Write=0;
PC_s=(ZF?
b00);
b000101:
b10);
//处理J型跳转指令
b00001)
begin
address=inst[25:
b000010:
beginw_r_s=2'
b11;
b000011:
b10;
寄存器堆模块:
module
Register_file(R_Addr_A,R_Addr_B,W_Addr,Write_Reg,W_Data,Clk,Reset,R_Data_A,R_Data_B);
input[4:
0]R_Addr_A;
0]R_Addr_B;
inputWrite_Reg;
inputClk;
inputReset;
output[31:
0]REG_Files[0:
31];
reg[5:
0]i;
initial//仿真过程中的初始化
for(i=0;
iv=31;
i二i+1)
REG_Files[i]=O;
assignR_Data_A=REG_Files[R_Addr_A];
assignR_Data_B=REG_Files[R_Addr_B];
always@(posedgeClkorposedgeReset)begin
if(Reset)
i<
=31;
i=i+1)
REG_Files[i]v=O;
if(Write_Reg&
W_Addr!
=0)
REG_Files[W_Addr]<
=W_Data;
end
ALU运算模块:
moduleALU(A,B,F,ALU_QZF,OF);
0]A,B;
input[2:
outputregZF,OF;
outputreg[31:
regC32;
OF=1'
b0;
C32=1'
case(ALU_OP)
3'
b000:
F=A&
B;
b001:
F=A|B;
b010:
F=AAB;
bO11:
F=~(A^B);
b100:
begin{C32,F}=A+B;
OF=A[31]AB[31]AF[31]AC32;
b101:
begin{C32,F}二A-B;
OF二A[31]AB[31]AF[31FC32;
end3'
b110:
if(A<
B)
F=1;
F=0;
b111:
F=B<
A;
if(F==0)
ZF=1;
ZF=0;
J!
仿真波形
Njme
Vtki*
曲饶
k■FIJI*]
•电M_R_Dala[11fl]
1
吃网II
IhO
Q
0000(X1悴259^353
三、电路图
顶层电路模块
SW(3:
D)
TOPLED
LED(7:
0)
elk100MH2
odk
nsl
■/
TOP_LED
TOPLED.1
顶层电路内部结构:
四、引脚配置(约束文件)
NET"
LED[7]"
LOC=T11;
LED[6]"
LOC=R11;
LED[5]"
LOC=N11;
LED[4]"
LOC=M11;
LED[3]"
LOC=V15;
LED[2]"
LOC=U15;
LED[1]"
LOC=V16;
LED[0]"
LOC=U16;
SW[3]"
LOC=M8;
SW[1]"
LOC=T9;
SW[01"
LOC=T10;
clk_100MHz"
LOC=V10;
oclk"
LOC=C9;
rst"
LOC=C4;
SW[2]"
LOC=V9;
五、思考与探索
(1)R-l-J型指令CPU实验结果记录表
序号
指令
执行结果
标志
结论
00004020
$8=0000_0000
正确
2
00004820
$9=0000_0000
3
200a0014
$10=0000_0014
4
8d2b0010
$11=0000_0010
5
010b4020
$8=0000_2222
6
21290004
$9=0000_0004
7
214affff
$10=000_0013
8
11400001
判断:
$10不为0
9
08000003
返回去执行地址为
0000_0010的指令,即序号4:
8d2b0010
ac0b0030
存储器地址:
00000030
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