How to interface FPGAs to microcontrollers.docx
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How to interface FPGAs to microcontrollers.docx
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HowtointerfaceFPGAstomicrocontrollers
HowtointerfaceFPGAstomicrocontrollers
RocendoBracamontesDelToro,Atmel
7/30/20082:
12PMEDT
AsmanyashalfofallembeddeddesignshaveanFPGAnexttoamicrocontroller.TheFPGAcanbeusedtoimplementanythingfromgluelogic,tocustomIP,toacceleratorsforcomputationallyintensivealgorithms.Bytakingonsomeoftheprocessingtasks,FPGAshelptoimprovesystemperformance,therebyfreeinguptheMCUfromcycle-intensivetasks.FPGAsalsoprovideexcellentperformancecharacteristicsandlotsofflexibilitytoaccommodatechangingstandards.
TherearetwobasicimplementationsofMCU-plus-FPGAdesigns:
puttingasoftMCUcoreintotheFPGAlogicstructureorusingastandardproductMCUwithadiscreteFPGA.PuttingasoftcoreintotheFPGAcanbeeffective,butitcanalsobeanexpensiveandpower-hungrywaytoimplementamicrocontrollerwhencomparedtoastandardproduct.Thisisespeciallytruewhenusinga32-bitARM-basedcore.Asaresult,onlyaboutone-thirdofFPGA-plus-MCUdesignsareimplementedwithanMCUcoreinsidetheFPGAlogic.Theremainingtwo-thirdsconsistofastandardproductmicrocontrollernexttoadiscreteFPGA.
NeitherstandardproductmicrocontrollersnorFPGAsweredevelopedtocommunicatewitheachotherefficiently.Theyevenusedifferentlanguages.Thus,interfacingthetwocanbeachallenge.FPGAsdonothaveanydedicatedlogicthatcommunicateswithmicrocontrollers.Thislogicmodulemustbedesignedfromscratch.Second,thecommunicationbetweenthemicrocontrollerandFPGAisasynchronous.SpecialcareisneededtoresynchronizetheMCUtotheFPGAclockdomain.Finally,thereisanissueofbottlenecks,bothattheinterfaceandontheMCUbus.TransferringinformationbetweentheMCUandtheFPGAusuallyrequirescyclesontheMCUbusandusuallytiesuptheresource(PIOorEBI)usedtoeffectthetransfer.CaremustbetakentoavoidbottleneckswithexternalSRAMorFlashandontheMCUbus.
TherearebasicallythreehardwareoptionsforinterfacingtheFPGAtotheMCU:
programmableI/O(PIO);externalbusinterface(EBI),ifavailable;and,finally,adedicatedinterfacebetweenbuiltintotheMCUbetweentheadvancedhigh-speedbus(AHB)andtheFPGA.Whichapproachtousedependsontheendapplicationandthedesiredresult.
PIOInterface
InterfacingtheMCUtotheFPGAviathePIOisrelativelysimpleforsimpledatatransfers,consistingofthetransferof32bitsofaddress,32bitsofdata,andsomecontrolsignalsforcontrol.Thisrequiresa32-bitPIOandanadditional2-bitsonanotherPIO(Fig1).
1.PIOinterfacetoFPGA.
(Clickthisimagetoviewalarger,moredetailedversion)
ForatransferofdatatotheFPGA,thedirectionofthebidirectionalbuffersinthePIOmustbesettooutput.ThesoftwarealgorithmthattransfersdatatotheFPGAisasfollows:
PIO_DATA=ADDRESS;//Passtheaddresstowrite
PIO_CTROL=START|WR;//Sendstartofaddresscycle
PIO_CTROL=CLEAR;//ClearPIOctrl,thisendstheaddresscycle
PIO_DATA=DATA;//Setdatatotransfer
PIO_CTROL=START;//DataisreadyinPIO
PIO_CTROL=CLEAR;//Thisendsthedatacycle
ReadingfromtheFPGAissimilar.Again,thedirectionofthebufferonthePIOmustfirstbesettooutputandthenchangedirectionstoinputtoreadthedatafromtheFPGA,thefollowingcodeisexecuted:
PIO_DATA=ADDRESS;//Settheaddresstoread
PIO_CTROL=START|RD;//Sendstartofaddresscycle
PIO_CTROL=CLEAR;//ClearPIOctrl,thisendstheaddresscycle
PIO_DATA_DIR=INPUT;//SetPIO-Datadirectionasinputtoreceivethedata
DELAY(WAIT_FOR_FPGA);//waitfortheFPGAtosendthedata
DATA_FROM_FPGA=*PIO_DATA;//ReaddatafromFPGA
Theabovealgorithmsareforabasictransfer,amoresophisticatedalgorithmisnecessarytoestablishapropercommunicationbetweentheARMmicrocontrollerandtheFPGA.Specialcareisnecessarytoensuretheacknowledgmentofdata,e.g.nodatahasbeenlostduetospeedorwaitcyclesoneachside.
Theaccesstimeiscalculatedasthesumof:
TAccess-PIO=t1+addressphase+t2+dataphase
UsingtheGCCcompilerwithmaximumoptimizations,thesystemtakesapproximately55AHBcyclestoperformthewriteoperationtotheFPGA(Fig2).
2.PIOwritetoFPGA.
(Clickthisimagetoviewalarger,moredetailedversion)
Assumingt2(waitforFPGAresponseready)isalsoaround25AHBcycles,thesystemtakesapproximately85AHBcyclesforareadoperationfromFPGA(Fig3).
3.PIOreadfromFPGA.
(Clickthisimagetoviewalarger,moredetailedversion)
TheinterfacefromtheMCUitselfisfairlysimpleandstraightforward.However,speciallogicmustbeimplementedintheFPGAtodecodeallthetrafficgeneratedbythePIO.Inthemajorityofcases,thetrafficfromthemicrocontrolleriscompletelyasynchronous.Asaresult,theFPGAmustbeabletooversamplethecontrolsignalsfromthemicrocontroller;otherwisetheFPGAwillmissthetimewindowandthetrafficwillnotarriveatthefinaldestinationinsidetheFPGA.
SincetheprocessoristheoneinchargeofkeepingthePIObusy,thereisanoverheadofprocessingtime.WhiletheCPUisengagedindatatransfers,itcannotdoanythingelse.Thus,thissolutionhasthepotentialtobogdownsystemprocessing.DMAisnotpossibleusingaPIOinterface,sothesoftwareprogrammermustlimitdatabandwidthtoallowforothercommunicationwiththeMCU.Forexample,ifthereisaroutinethatdemands100%oftheprocessorscyclesrunningconcurrentlywithaserial(SPI,USARTorTWI)transfertoorfromtheFPGA,thenoneofthesetwoprocessesmustwait.IfthedatagoingtoorcomingfromtheFPGAisnotbufferedontime,itwillprobablybeoverrunbythenextbyte/wordofdata.Inessence,theembeddedprocessorbecomesaglorifieddatamover.
InterfacingthroughtheExternalBusInterface(EIB)
Many32-bitmicrocontrollershaveanexternalbusinterface(EBI)module,whichisdesignedtotransferdatabetweenexternaldevicesandthememorycontrollersonARM-baseddevices.Theseexternalmemorycontrollersarecapableofhandlingseveraltypesofexternalmemoryandperipheraldevices,suchasSRAM,PROM,EPROM,EEPROM,flash,andSDRAM.
TheEBIcanalsobeusedtointerfacetoFPGAsaslongastheFPGAcanhandlethepredefinedmemoryinterfaces.Usingthestaticmemoryinterface(SRAM)ontheEBIispreferableforFPGAcommunicationbecauseitissimpleandmostdesignersarefamiliarwithit.AswiththePIOinterface,theFPGAwillhavetoincludeamodulethatunderstandstheSRAMtimingandisabletoproducearesponsebacktothemicrocontroller(Fig4).
4.EBI-SMCinterface.
(Clickthisimagetoviewalarger,moredetailedversion)
Fig5showsthestandardreadtimingfortheEBIusingtheSMCmemoryinterface,whileFig6showsthestandardwritecycle.
5.EBI-SMCreadcycle.
(Clickthisimagetoviewalarger,moredetailedversion)
6.EBI-SMCwritecycle.
(Clickthisimagetoviewalarger,moredetailedversion)
Note:
ThesetimingwaveformsarethedefaultforSMCspecification.Allparametersshownareprogrammablebasedonthespeedoftheexternaldevice.
AnEBIinterfaceisfasterthanPIObecausetheEBIhasitsownI/Oinplaceandmostofthesignalsareparallel.However,iftheexternaldeviceissloworintroduceswaitstates,theEBI'sspeedadvantagecouldbecompromised.
LikethePIOinterface,theEBIinterfacemustbedrivenbytheprocessororanotherAHBmaster.Thus,theachievablebandwidthontheEBIisalsodependentonsoftwareanddependsonhowmuchprocessortimeisavailabletoit.Certainlytherecouldbeabandwidthlimitation.Thisagainpotentiallylimitstheembeddedprocessorincarryingoutothersystemfunctionsthatitwasdesignedtodo.
UsingadedicatedFPGAinterfaceontheMCU
ARM7-basedmicrocontrollersareavailablewithaspecialinterfacethatallowstheFPGAtodirectlyaccesstotheMCU'sinternalAHBbuswithDMAaccessviatwoAHBmastersandfourAHBslaves.OneextraAHBslavemaybeusedtore-maptheROMusinganexternalZBTRAMthroughtheFPGAwithaprogrammableROMre-mapfeatureatstartup.
TheinterfacealsogivestheFPGAaccesstofourteenadvancedperipheralbus(APB)slaves,twoDMAfullduplexchannels,uptothirteenpriorityencodedinterrupts(IRQs),twonon-encodedIRQsforDMAtransfersand32-bitsofsharedprogrammableI/Os.TheFPGAinterfaceaccessestheAHBthroughthepre-definedmastersandslavesonthemicrocontroller(Fig7).
7.MCUwithdedicatedFPGAinterface.
(Clickthisimagetoviewalarger,moredetailedversion)
TheFPGAinterfaceisbasedonseveralserializersthatencodeanddecodeallthetrafficbetweenthemicrocontrollerandtheFPGA.Inordertohaveapropercommunicationandsynchronizationbetweenbothdevices,thefollowingrequirementsmustbeinplace:
∙TheFPGAmustbecapableofhandlingskewclockbalancingandlatencycancellation.IntheXilinxFPGAfamilies,theusageofDCM's(DigitalClockManager)ismandatorytohandleallthelatencycancellationandrequiredclocksgeneration.AlteradevicesrequiretheuseofPLL's.TheFPGAmustalsoprovidetheconfigurationmodesandresettothemicrocontroller'sbuilt-ininterface.Itmustprovidetheserialcommunicationclocktothemicrocontroller,whichmayhaveafrequencyofupto100MHzforcommercialrangedevices.TheratiobetweentheinternalARM7clockandtheserialclockshouldbeintheorderof0.8orlower(ARMClk/SerialClk).
∙TheFPGA-interfaceisbasedonasetofmodulesthatencodeanddecodetheinternalAHBtransactions.Theencoded/decodeddataistransferredthroughMPIO'susingdedicatedserializersforeachmas
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