数字电子技术(Floyd 第十版)课件Chapter 7.ppt
- 文档编号:9642006
- 上传时间:2023-05-20
- 格式:PPT
- 页数:47
- 大小:2.45MB
数字电子技术(Floyd 第十版)课件Chapter 7.ppt
《数字电子技术(Floyd 第十版)课件Chapter 7.ppt》由会员分享,可在线阅读,更多相关《数字电子技术(Floyd 第十版)课件Chapter 7.ppt(47页珍藏版)》请在冰点文库上搜索。
,DigitalFundamentalsTenthEditionFloyd,Chapter6,2008PearsonEducation,Quiz2(20minutes),RefertoKarnaughmap:
WritethestandardSOP(SumofProduct)formfortheoutput(5points)WritethestandardPOS(productofSum)formfortheoutput(5points)WritetheminimumSOPform.Drawthecircuit.(10points)WritetheminimumPOSform.Drawthecircuit(10points),Basicrulesofbinaryadditionareperformedbyahalfadder,whichhastwobinaryinputs(AandB)andtwobinaryoutputs(CarryoutandSum).,Summary,Half-Adder,Theinputsandoutputscanbesummarizedonatruthtable.,Thelogicsymbolandequivalentcircuitare:
Summary,Full-Adder,Bycontrast,afulladderhasthreebinaryinputs(A,B,andCarryin)andtwobinaryoutputs(CarryoutandSum).Thetruthtablesummarizestheoperation.,Afull-addercanbeconstructedfromtwohalfaddersasshown:
A,B,S,Cout,S,A,B,Sum,Cout,Cin,A,B,S,Cout,S,Cin,Symbol,Summary,Full-Adder,Example,Solution,Forthegiveninputs,determinetheintermediateandfinaloutputsofthefulladder.,1,1,0,1,0,Thefirsthalf-adderhasinputsof1and0;thereforetheSum=1andtheCarryout=0.,Thesecondhalf-adderhasinputsof1and1;thereforetheSum=0andtheCarryout=1.,TheORgatehasinputsof1and0,thereforethefinalcarryout=1.,1,0,1,Sum,Cout,Summary,Full-Adder,Noticethattheresultfromthepreviousexamplecanbereaddirectlyonthetruthtableforafulladder.,Summary,ParallelAdders,Fulladdersarecombinedintoparalleladdersthatcanaddbinarynumberswithmultiplebits.A4-bitadderisshown.,Theoutputcarry(C4)isnotreadyuntilitpropagatesthroughallofthefulladders.Thisiscalledripplecarry,delayingtheadditionprocess.,Summary,ParallelAdders,Thelogicsymbolfora4-bitparalleladderisshown.This4-bitadderincludesacarryin(labeled(C0)andaCarryout(labeledC4).,The74LS283isanexample.Itfeatureslook-aheadcarry,whichaddslogictominimizetheoutputcarrydelay.Forthe74LS283,themaximumdelaytotheoutputcarryis17ns.,Summary,Comparators,Thefunctionofacomparatoristocomparethemagnitudesoftwobinarynumberstodeterminetherelationshipbetweenthem.Inthesimplestform,acomparatorcantestforequalityusingXNORgates.,Example,Solution,Howcouldyoutesttwo4-bitnumbersforequality?
ANDtheoutputsoffourXNORgates.,A1B1,A2B2,A3B3,A4B4,Output,Summary,Comparators,ICcomparatorsprovideoutputstoindicatewhichofthenumbersislargeroriftheyareequal.Thebitsarenumberedstartingat0,ratherthan1asinthecaseofadders.Cascadinginputsareprovidedtoexpandthecomparatortolargernumbers.,Outputs,TheICshownisthe4-bit74LS85.,Summary,Comparators,ICcomparatorscanbeexpandedusingthecascadinginputsasshown.ThelowestordercomparatorhasaHIGHontheA=Binput.,Summary,Decoders,Adecoderisalogiccircuitthatdetectsthepresenceofaspecificcombinationofbitsatitsinput.Twosimpledecodersthatdetectthepresenceofthebinarycode0011areshown.ThefirsthasanactiveHIGHoutput;thesecondhasanactiveLOWoutput.,A1,A0,A2,A3,X,ActiveHIGHdecoderfor0011,A1,A0,A2,A3,X,ActiveLOWdecoderfor0011,Summary,Decoders,Assumetheoutputofthedecodershownisalogic1.Whataretheinputstothedecoder?
Question,Summary,Decoders,ICdecodershavemultipleoutputstodecodeanycombinationofinputs.Forexamplethebinary-to-decimaldecodershownherehas16outputsoneforeachcombinationofbinaryinputs.,Question,Fortheinputshown,whatistheoutput?
Summary,Decoders,Aspecificintegratedcircuitdecoderisthe74HC154(shownasa4-to-16decoder).ItincludestwoactiveLOWchipselectlineswhichmustbeattheactiveleveltoenabletheoutputs.Theselinescanbeusedtoexpandthedecodertolargerinputs.,CS2,A1,A0,A2,A3,CS1,X/Y,EN,74HC154,Summary,Decoders,The74LS138isa3-to-8decoderwiththreechipselectinputs(twoactiveLOW,oneactiveHIGH).InthisMultisimcircuit,thewordgenerator(XWG1)issetupasanupcounter.Thelogicanalyzer(XLA1)comparestheinputandoutputsofthedecoder.,Inputsareblue,outputsarered.,Summary,Decoders,Inputsareblue,outputsarered.,Question,Howwillthewaveformschangeifthewordgeneratorisconfiguredasadowncounterinsteadofanupcounter?
Summary,Decoders,Thechipselectinputscanbeusedtoexpandadecoder.Inthiscircuit,two74LS138sareconfiguredasa16linedecoder.NoticehowtheMSBisconnectedtooneactiveLOWandoneactiveHIGHchipselect.,Thenextslideshowsthelogicanalyzeroutput,Summary,Decoders,Question,Isthewordgeneratorsetasanupcounteroradowncounter?
(Theleastsignificantdecoderoutputatthetop).,Itisanupcounter.,Summary,Decoders,BCD-to-decimaldecodersacceptabinarycodeddecimalinputandactivateoneoftenpossibledecimaldigitindications.,A1,A0,A2,A3,Example,Solution,Assumetheinputstothe74HC42decoderarethesequence0101,0110,0011,and0010.Describetheoutput.,AlllinesareHIGHexceptforoneactiveoutput,whichisLOW.Theactiveoutputsare5,6,3,and2inthatorder.,Summary,BCDDecoder/Driver,Anotherusefuldecoderisthe74LS47.ThisisaBCD-to-sevensegmentdisplaywithactiveLOWoutputs.,Thea-goutputsaredesignedformuchhighercurrentthanmostdevices(hencetheworddriverinthename).,BCDinputs,Outputstosevensegmentdevice,GND,VCC,BCD/7-seg,BI/RBO,BI/RBO,LT,RBI,LT,RBI,74LS47,Summary,BCDDecoder/Driver,Herethe7447AisanconnectedtoanLEDsevensegmentdisplay.Noticethecurrentlimitingresistors,requiredtopreventoverdrivingtheLEDdisplay.,Summary,BCDDecoder/Driver,Blanked,Blanked,Dependingonthedisplaytype,currentlimitingresistorsmayberequired.,Summary,BCDDecoder/Driver,Blanked,Blanked,Decimalpoint,Summary,Encoders,Anencoderacceptsanactivelogiclevelononeofitsinputsandconvertsittoacodedoutput,suchasBCDorbinary.,ThedecimaltoBCDisanencoderwithaninputforeachofthetendecimaldigitsandfouroutputsthatrepresenttheBCDcodefortheactivedigit.Thebasiclogicdiagramisshown.ThereisnozeroinputbecausetheoutputsareallLOWwhentheinputiszero.,A1,A0,A2,A3,1,2,3,4,5,6,7,8,9,Summary,Encoders,A1,A0,A2,A3,Example,Solution,Showhowthedecimal-to-BCDencoderconvertsthedecimalnumber3intoaBCD0011.,ThetoptwoORgateshaveonesasindicatedwiththeredlines.Thustheoutputis0111.,1,2,3,4,5,6,7,8,9,0,0,1,1,Summary,Encoders,The74HC147isanexampleofanICencoder.Itishastenactive-LOWinputsandconvertstheactiveinputtoanactive-LOWBCDoutput.,Thisdeviceisoffersadditionalflexibilityinthatitisapriorityencoder.Thismeansthatifmorethanoneinputisactive,theonewiththehighestorderdecimaldigitwillbeactive.,Decimalinput,BCDoutput,GND,VCC,HPRI/BCD,74HC147,Thenextslideshowsanapplication,Summary,Encoders,VCC,BCDcomplementofkeypress,Keyboardencoder,HPRI/BCD,74HC147,Thezerolineisnotneededbytheencoder,butmaybeusedbyothercircuitstodetectakeypress.,Summary,Codeconverters,Therearevariouscodeconvertersthatchangeonecodetoanother.Twoexamplesarethefourbitbinary-to-GrayconverterandtheGray-to-binaryconverter.,Example,Showtheconversionofbinary0111toGrayandback.,Solution,0,0,0,1,1,1,1,0,0,0,1,0,0,1,1,1,Amultiplexer(MUX)selectsonedatalinefromtwoormoreinputlinesandroutesdatafromtheselectedlinetotheoutput.Theparticulardatalinethatisselectedisdeterminedbytheselectinputs.,Summary,Multiplexers,Twoselectlinesareshownheretochooseanyofthefourdatainputs.,Dataselect,Datainputs,Dataoutput,D1,D0,D2,D3,S1,S0,Question,WhichdatalineisselectedifS1S0=10?
D2,1,0,Ademultiplexer(DEMUX)performstheoppositefunctionfromaMUX.Itswitchesdatafromoneinputlinetotwoormoredatalinesdependingontheselectinputs.,The74LS138wasintroducedpreviouslyasadecoderbutcanalsoserveasaDEMUX.WhenconnectedasaDEMUX,dataisappliedtooneoftheenableinputs,androutedtotheselectedoutputlinedependingontheselectvariables.Notethattheoutputsareactive-LOWasillustratedinthefollowingexample,Summary,Demultiplexers,74LS138,Dataselectlines,Enableinputs,Dataoutputs,Determinetheoutputs,giventheinputsshown.,Summary,Demultiplexers,Example,74LS138,Dataselectlines,Enableinputs,Dataoutputs,A,0,Y,0,Y,1,Y,2,Y,3,Y,4,Y,5,Y,6,Y,7,A,1,A,2,G,1,G,2A,G,2B,LOW,LOW,Theoutputlogicisoppositetotheinputbecauseoftheactive-LOWconvention.(Redshowstheselectedline).,Solution,Summary,ParityGenerators/Checkers,Parityisanerrordetectionmethodthatusesanextrabitappendedtoagroupofbitstoforcethemtobeeitheroddoreven.Inevenparity,thetotalnumberofonesiseven;inoddparitythetotalnumberofonesisodd.,11010011,Swithoddparity=,Swithevenparity=,01010011,Example,TheASCIIletterSis1010011.ShowtheparitybitfortheletterSwithoddandevenparity.,Solution,Summary,ParityGenerators/Checkers,The74LS280canbeusedtogenerateaparitybitortocheckanincomingdatastreamforevenoroddparity.,Checker:
The74LS280cantestcodeswithupto9bits.TheevenoutputwillnormallybeHIGHifthedatalineshaveevenparity;otherwiseitwillbeLOW.Likewise,theoddoutputwillnormallybeHIGHifthedatalineshaveoddparity;otherwiseitwillbeLOW.,Generator:
Togenerateevenparity,theparitybitistakenfromtheoddparityoutput.Togenerateoddparity,theoutputistakenfromtheevenparityoutput.,74LS280,Datainputs,SEven,SOdd,SelectedKeyTerms,Full-adderCascadingRipplecarryLook-aheadcarry,Adigitalcircuitthataddstwobitsandaninputcarrybittoproduceasumandanoutputcarry.,Connectingtwoormoresimilardevicesinamannerthatexpandsthecapabilityofonedevice.,Amethodofbinaryadditioninwhichtheoutputcarryfromeachadderbecomestheinputcarryofthenexthigherorderadder.,Ametho
- 配套讲稿:
如PPT文件的首页显示word图标,表示该PPT已包含配套word讲稿。双击word图标可打开word文档。
- 特殊限制:
部分文档作品中含有的国旗、国徽等图片,仅作为作品整体效果示例展示,禁止商用。设计者仅对作品中独创性部分享有著作权。
- 关 键 词:
- 数字电子技术Floyd 第十版课件Chapter 数字 电子技术 Floyd 第十 课件 Chapter
![提示](https://static.bingdoc.com/images/bang_tan.gif)